diff options
| author | Amy Zhang <Amy.Zhang@amd.com> | 2017-05-31 16:53:01 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-09-26 18:07:50 -0400 |
| commit | 9f72f51d701cd2dd87a157d972650924fe91ec80 (patch) | |
| tree | 2706bf28e4fb81a5dd40e55ae0b999e6715316ac /drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | |
| parent | 1a2c82a2f161f68deb5f0519c315bfc92ede8e01 (diff) | |
| download | linux-9f72f51d701cd2dd87a157d972650924fe91ec80.tar.gz linux-9f72f51d701cd2dd87a157d972650924fe91ec80.tar.bz2 linux-9f72f51d701cd2dd87a157d972650924fe91ec80.zip | |
drm/amd/display: Refactor to call set PSR wait loop in dce_dmcu instead of dce_clocks
Signed-off-by: Amy Zhang <Amy.Zhang@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 66 |
1 files changed, 64 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c index 03b51e256e21..0fe3ee8e29d3 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c @@ -48,7 +48,9 @@ #define PSR_ENABLE 0x20 #define PSR_EXIT 0x21 #define PSR_SET 0x23 +#define PSR_SET_WAITLOOP 0x31 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x00000001L +unsigned int cached_wait_loop_number = 0; bool dce_dmcu_load_iram(struct dmcu *dmcu, unsigned int start_offset, @@ -252,6 +254,34 @@ static void dce_dmcu_setup_psr(struct dmcu *dmcu, REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); } +static void dce_psr_wait_loop( + struct dmcu *dmcu, + unsigned int wait_loop_number) +{ + struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); + union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1; + + /* waitDMCUReadyForCmd */ + REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 100); + + masterCmdData1.u32 = 0; + masterCmdData1.bits.wait_loop = wait_loop_number; + cached_wait_loop_number = wait_loop_number; + dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32); + + /* setDMCUParam_Cmd */ + REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP); + + /* notifyDMCUMsg */ + REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); +} + +static void dce_get_psr_wait_loop(unsigned int *psr_wait_loop_number) +{ + *psr_wait_loop_number = cached_wait_loop_number; + return; +} + #if defined(CONFIG_DRM_AMD_DC_DCN1_0) bool dcn10_dmcu_load_iram(struct dmcu *dmcu, unsigned int start_offset, @@ -464,13 +494,43 @@ static void dcn10_dmcu_setup_psr(struct dmcu *dmcu, REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); } +static void dcn10_psr_wait_loop( + struct dmcu *dmcu, + unsigned int wait_loop_number) +{ + struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); + union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1; + + /* waitDMCUReadyForCmd */ + REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 100); + + masterCmdData1.u32 = 0; + masterCmdData1.bits.wait_loop = wait_loop_number; + cached_wait_loop_number = wait_loop_number; + dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32); + + /* setDMCUParam_Cmd */ + REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP); + + /* notifyDMCUMsg */ + REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); +} + +static void dcn10_get_psr_wait_loop(unsigned int *psr_wait_loop_number) +{ + *psr_wait_loop_number = cached_wait_loop_number; + return; +} + #endif static const struct dmcu_funcs dce_funcs = { .load_iram = dce_dmcu_load_iram, .set_psr_enable = dce_dmcu_set_psr_enable, .setup_psr = dce_dmcu_setup_psr, - .get_psr_state = dce_get_dmcu_psr_state + .get_psr_state = dce_get_dmcu_psr_state, + .set_psr_wait_loop = dce_psr_wait_loop, + .get_psr_wait_loop = dce_get_psr_wait_loop }; #if defined(CONFIG_DRM_AMD_DC_DCN1_0) @@ -478,7 +538,9 @@ static const struct dmcu_funcs dcn10_funcs = { .load_iram = dcn10_dmcu_load_iram, .set_psr_enable = dcn10_dmcu_set_psr_enable, .setup_psr = dcn10_dmcu_setup_psr, - .get_psr_state = dcn10_get_dmcu_psr_state + .get_psr_state = dcn10_get_dmcu_psr_state, + .set_psr_wait_loop = dcn10_psr_wait_loop, + .get_psr_wait_loop = dcn10_get_psr_wait_loop }; #endif |