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authorCharlene Liu <charlene.liu@amd.com>2017-03-24 16:54:02 -0400
committerAlex Deucher <alexander.deucher@amd.com>2017-09-26 17:21:13 -0400
commitfd8cc371ede63d69cf69bb3a8a9a005d91ae023f (patch)
treed86c21a67a76cb5d3f499614b49faf7930854708 /drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
parente902915507bd20115e1e21bc99ea36ea7986cebc (diff)
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drm/amd/display: voltage request related change
Signed-off-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c27
1 files changed, 14 insertions, 13 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
index 263f8900e39c..b4fd02219c2c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
@@ -495,6 +495,7 @@ static void dce_clock_read_ss_info(struct dce_disp_clk *clk_dce)
}
}
+
static bool dce_apply_clock_voltage_request(
struct display_clock *clk,
enum dm_pp_clock_type clocks_type,
@@ -502,6 +503,7 @@ static bool dce_apply_clock_voltage_request(
bool pre_mode_set,
bool update_dp_phyclk)
{
+ bool send_request = false;
struct dm_pp_clock_for_voltage_req clock_voltage_req = {0};
switch (clocks_type) {
@@ -522,9 +524,8 @@ static bool dce_apply_clock_voltage_request(
switch (clocks_type) {
case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
if (clocks_in_khz > clk->cur_clocks_value.dispclk_in_khz) {
- dm_pp_apply_clock_for_voltage_request(
- clk->ctx, &clock_voltage_req);
clk->cur_clocks_value.dispclk_notify_pplib_done = true;
+ send_request = true;
} else
clk->cur_clocks_value.dispclk_notify_pplib_done = false;
/* no matter incrase or decrase clock, update current clock value */
@@ -532,9 +533,8 @@ static bool dce_apply_clock_voltage_request(
break;
case DM_PP_CLOCK_TYPE_PIXELCLK:
if (clocks_in_khz > clk->cur_clocks_value.max_pixelclk_in_khz) {
- dm_pp_apply_clock_for_voltage_request(
- clk->ctx, &clock_voltage_req);
clk->cur_clocks_value.pixelclk_notify_pplib_done = true;
+ send_request = true;
} else
clk->cur_clocks_value.pixelclk_notify_pplib_done = false;
/* no matter incrase or decrase clock, update current clock value */
@@ -542,9 +542,8 @@ static bool dce_apply_clock_voltage_request(
break;
case DM_PP_CLOCK_TYPE_DISPLAYPHYCLK:
if (clocks_in_khz > clk->cur_clocks_value.max_non_dp_phyclk_in_khz) {
- dm_pp_apply_clock_for_voltage_request(
- clk->ctx, &clock_voltage_req);
clk->cur_clocks_value.phyclk_notigy_pplib_done = true;
+ send_request = true;
} else
clk->cur_clocks_value.phyclk_notigy_pplib_done = false;
/* no matter incrase or decrase clock, update current clock value */
@@ -554,29 +553,30 @@ static bool dce_apply_clock_voltage_request(
ASSERT(0);
break;
}
+
} else {
switch (clocks_type) {
case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
if (!clk->cur_clocks_value.dispclk_notify_pplib_done)
- dm_pp_apply_clock_for_voltage_request(
- clk->ctx, &clock_voltage_req);
+ send_request = true;
break;
case DM_PP_CLOCK_TYPE_PIXELCLK:
if (!clk->cur_clocks_value.pixelclk_notify_pplib_done)
- dm_pp_apply_clock_for_voltage_request(
- clk->ctx, &clock_voltage_req);
+ send_request = true;
break;
case DM_PP_CLOCK_TYPE_DISPLAYPHYCLK:
if (!clk->cur_clocks_value.phyclk_notigy_pplib_done)
- dm_pp_apply_clock_for_voltage_request(
- clk->ctx, &clock_voltage_req);
+ send_request = true;
break;
default:
ASSERT(0);
break;
}
}
-
+ if (send_request) {
+ dm_pp_apply_clock_for_voltage_request(
+ clk->ctx, &clock_voltage_req);
+ }
if (update_dp_phyclk && (clocks_in_khz >
clk->cur_clocks_value.max_dp_phyclk_in_khz))
clk->cur_clocks_value.max_dp_phyclk_in_khz = clocks_in_khz;
@@ -584,6 +584,7 @@ static bool dce_apply_clock_voltage_request(
return true;
}
+
static const struct display_clock_funcs dce120_funcs = {
.get_dp_ref_clk_frequency = dce_clocks_get_dp_ref_freq,
.apply_clock_voltage_request = dce_apply_clock_voltage_request,