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| author | Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> | 2019-11-06 14:48:35 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-11-13 15:29:44 -0500 |
| commit | b86a1aa36a92bcfbc062c5e99c1d084f27f25bab (patch) | |
| tree | 8eee374e066e9e51a4bf9aaa36b507aa5c38bf45 /drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h | |
| parent | aca935c7cc866a935a61769c9e9782dd834a8502 (diff) | |
| download | linux-b86a1aa36a92bcfbc062c5e99c1d084f27f25bab.tar.gz linux-b86a1aa36a92bcfbc062c5e99c1d084f27f25bab.tar.bz2 linux-b86a1aa36a92bcfbc062c5e99c1d084f27f25bab.zip | |
drm/amd/display: rename DCN1_0 kconfig to DCN
Since dcn20 and dcn21 are under dcn1 it doesnt make sense to
have it named dcn1.
Change it to "dcn" to make it generic
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h index 8d0d07db5190..51bd25079606 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h @@ -97,7 +97,7 @@ CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\ CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh) -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) +#if defined(CONFIG_DRM_AMD_DC_DCN) #define CS_COMMON_REG_LIST_DCN1_0(index, pllid) \ SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ |