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| author | Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> | 2020-09-29 14:52:09 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-10-12 14:02:51 -0400 |
| commit | 36d26912e8d854853e3cdb300664db274a6636cf (patch) | |
| tree | 7bfd642a153170007b90816aae1bb561d8b66481 /drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h | |
| parent | 4da678390890c7cf99e068ecd9d7ee5bf0d5290b (diff) | |
| download | linux-36d26912e8d854853e3cdb300664db274a6636cf.tar.gz linux-36d26912e8d854853e3cdb300664db274a6636cf.tar.bz2 linux-36d26912e8d854853e3cdb300664db274a6636cf.zip | |
drm/amd/display: Add support for DCN302 (v2)
- add DCN302 resource, irq service, dmub loader,
- handle DC_VERSION_DCN_3_02
- define DCN302 power gating functions
- handle DCN302 in GPIO files
- define I2C regs
- add CONFIG_DRM_AMD_DC_DCN3_02 guard
v2: rebase fixes (Alex)
Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h index 41e6f7ea2138..09d25775d71f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h @@ -125,6 +125,26 @@ SRII(PIXEL_RATE_CNTL, OTG, 3) #endif +#if defined(CONFIG_DRM_AMD_DC_DCN3_02) +#define CS_COMMON_REG_LIST_DCN3_02(index, pllid) \ + SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ + SRII(PHASE, DP_DTO, 0),\ + SRII(PHASE, DP_DTO, 1),\ + SRII(PHASE, DP_DTO, 2),\ + SRII(PHASE, DP_DTO, 3),\ + SRII(PHASE, DP_DTO, 4),\ + SRII(MODULO, DP_DTO, 0),\ + SRII(MODULO, DP_DTO, 1),\ + SRII(MODULO, DP_DTO, 2),\ + SRII(MODULO, DP_DTO, 3),\ + SRII(MODULO, DP_DTO, 4),\ + SRII(PIXEL_RATE_CNTL, OTG, 0),\ + SRII(PIXEL_RATE_CNTL, OTG, 1),\ + SRII(PIXEL_RATE_CNTL, OTG, 2),\ + SRII(PIXEL_RATE_CNTL, OTG, 3),\ + SRII(PIXEL_RATE_CNTL, OTG, 4) + +#endif #define CS_COMMON_MASK_SH_LIST_DCN2_0(mask_sh)\ CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\ CS_SF(DP_DTO0_MODULO, DP_DTO0_MODULO, mask_sh),\ |