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authorCharlene Liu <charlene.liu@amd.com>2017-03-02 21:18:03 -0500
committerAlex Deucher <alexander.deucher@amd.com>2017-09-26 17:18:11 -0400
commite8c963d6d970220ab33f4197ab4dea18c1615e52 (patch)
treebd1ee2337e039b33682579a831088ac70d3b2afe /drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
parentece4f358cb57c33089daaea1d86c62fa924060d1 (diff)
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drm/amd/display: refclock from bios firmwareInfoTable
Signed-off-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c17
1 files changed, 6 insertions, 11 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
index a2a2ecf8d077..1d6a9da45ba6 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -1230,17 +1230,12 @@ bool dce110_clk_src_construct(
goto unexpected_failure;
}
- if (clk_src->ref_freq_khz == 48000) {
- calc_pll_cs_init_data_hdmi.
- min_override_input_pxl_clk_pll_freq_khz = 24000;
- calc_pll_cs_init_data_hdmi.
- max_override_input_pxl_clk_pll_freq_khz = 48000;
- } else if (clk_src->ref_freq_khz == 100000) {
- calc_pll_cs_init_data_hdmi.
- min_override_input_pxl_clk_pll_freq_khz = 25000;
- calc_pll_cs_init_data_hdmi.
- max_override_input_pxl_clk_pll_freq_khz = 50000;
- }
+
+ calc_pll_cs_init_data_hdmi.
+ min_override_input_pxl_clk_pll_freq_khz = clk_src->ref_freq_khz/2;
+ calc_pll_cs_init_data_hdmi.
+ max_override_input_pxl_clk_pll_freq_khz = clk_src->ref_freq_khz;
+
if (!calc_pll_max_vco_construct(
&clk_src->calc_pll_hdmi, &calc_pll_cs_init_data_hdmi)) {