diff options
| author | Alex Deucher <alexander.deucher@amd.com> | 2020-11-02 15:37:34 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-11-04 17:11:37 -0500 |
| commit | 20f2ffe504728612d7b0c34e4f8280e34251e704 (patch) | |
| tree | ab97de569be30e009ba6e5087f3f6c775167e46c /drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | |
| parent | aeee2a48ec9239790b7c9a5c14dfb2a12554322f (diff) | |
| download | linux-20f2ffe504728612d7b0c34e4f8280e34251e704.tar.gz linux-20f2ffe504728612d7b0c34e4f8280e34251e704.tar.bz2 linux-20f2ffe504728612d7b0c34e4f8280e34251e704.zip | |
drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3)
Avoids confusion in configurations.
v2: fix build when CONFIG_DRM_AMD_DC_DCN is disabled
v3: rebase on latest code
Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> (v1)
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c index 589c7fb71480..fb733f573715 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c @@ -1004,7 +1004,7 @@ static bool get_pixel_clk_frequency_100hz( return false; } -#if defined(CONFIG_DRM_AMD_DC_DCN3_0) +#if defined(CONFIG_DRM_AMD_DC_DCN) /* this table is use to find *1.001 and /1.001 pixel rates from non-precise pixel rate */ const struct pixel_rate_range_table_entry video_optimized_pixel_rates[] = { // /1.001 rates @@ -1073,7 +1073,7 @@ static const struct clock_source_funcs dcn20_clk_src_funcs = { .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz }; -#if defined(CONFIG_DRM_AMD_DC_DCN3_0) +#if defined(CONFIG_DRM_AMD_DC_DCN) static bool dcn3_program_pix_clk( struct clock_source *clock_source, struct pixel_clk_params *pix_clk_params, @@ -1538,7 +1538,7 @@ bool dcn20_clk_src_construct( return ret; } -#if defined(CONFIG_DRM_AMD_DC_DCN3_0) +#if defined(CONFIG_DRM_AMD_DC_DCN) bool dcn3_clk_src_construct( struct dce110_clk_src *clk_src, struct dc_context *ctx, @@ -1556,7 +1556,7 @@ bool dcn3_clk_src_construct( } #endif -#if defined(CONFIG_DRM_AMD_DC_DCN3_01) +#if defined(CONFIG_DRM_AMD_DC_DCN) bool dcn301_clk_src_construct( struct dce110_clk_src *clk_src, struct dc_context *ctx, |