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| author | Chris Park <chris.park@amd.com> | 2024-11-15 15:44:52 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2024-12-02 18:35:32 -0500 |
| commit | 0c0a19430bfdfedab437e77b9262e8e62ced384e (patch) | |
| tree | ed694121e45c16cc6b9045e8fd7b122c1e4cfb66 /drivers/gpu/drm/amd/display/dc/dc_spl_translate.c | |
| parent | a29997b7ac1f5c816b543e0c56aa2b5b56baac24 (diff) | |
| download | linux-0c0a19430bfdfedab437e77b9262e8e62ced384e.tar.gz linux-0c0a19430bfdfedab437e77b9262e8e62ced384e.tar.bz2 linux-0c0a19430bfdfedab437e77b9262e8e62ced384e.zip | |
drm/amd/display: Add hblank borrowing support
[WHY]
Some DSC timing failed at bandwidth validation due to hactive
can't be evenly divided on each ODM segment.
[HOW]
Borrow from hblank to increase hactive to support these timing.
Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Chris Park <chris.park@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dc_spl_translate.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dc_spl_translate.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c b/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c index c8d8e335fa37..0e310fd48b5c 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c +++ b/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c @@ -120,7 +120,7 @@ void translate_SPL_in_params_from_pipe_ctx(struct pipe_ctx *pipe_ctx, struct spl spl_in->odm_slice_index = resource_get_odm_slice_index(pipe_ctx); // Make spl input basic out info output_size width point to stream h active spl_in->basic_out.output_size.width = - stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; + stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right + pipe_ctx->hblank_borrow; // Make spl input basic out info output_size height point to v active spl_in->basic_out.output_size.height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top; |