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| author | Zhan Liu <zhan.liu@amd.com> | 2021-09-25 00:01:48 -0700 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-10-04 15:22:57 -0400 |
| commit | 3f68c01be9a2227de1e190317fe34a6fb835a094 (patch) | |
| tree | da294c7baf14e182acf528fe663e1af4c5e113ed /drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | |
| parent | 0ad53fe3ae82443c74ff8cfd7bd13377cc1134a3 (diff) | |
| download | linux-3f68c01be9a2227de1e190317fe34a6fb835a094.tar.gz linux-3f68c01be9a2227de1e190317fe34a6fb835a094.tar.bz2 linux-3f68c01be9a2227de1e190317fe34a6fb835a094.zip | |
drm/amd/display: add cyan_skillfish display support
[Why]
add display related cyan_skillfish files in.
makefile controlled by CONFIG_DRM_AMD_DC_DCN201 flag.
v2: squash in clang fixes from Harry, Nathan
v3: squash in missing CONFIG_DRM_AMD_DC check (Alex)
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Signed-off-by: Zhan Liu <zhan.liu@amd.com>
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Jun Lei <jun.lei@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c index bb31541f8072..421f5135b701 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c @@ -39,6 +39,7 @@ #include "dcn10/rv2_clk_mgr.h" #include "dcn20/dcn20_clk_mgr.h" #include "dcn21/rn_clk_mgr.h" +#include "dcn201/dcn201_clk_mgr.h" #include "dcn30/dcn30_clk_mgr.h" #include "dcn301/vg_clk_mgr.h" #include "dcn31/dcn31_clk_mgr.h" @@ -256,6 +257,12 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); return &clk_mgr->base; } +#if defined(CONFIG_DRM_AMD_DC_DCN201) + if (asic_id.chip_id == DEVICE_ID_NV_13FE) { + dcn201_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); + return &clk_mgr->base; + } +#endif dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); return &clk_mgr->base; } |