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authorJude Shih <shenshih@amd.com>2021-04-20 10:19:37 +0800
committerAlex Deucher <alexander.deucher@amd.com>2021-05-10 18:06:44 -0400
commit81927e2808be5adace93c2012d45d6938d3a7aa0 (patch)
tree95f90e9a665f319d77ff5700d82870673bb47949 /drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
parent7f63d8a1ad37a481dba7e721c3510025bdb897d4 (diff)
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drm/amd/display: Support for DMUB AUX
[WHY] To process AUX transactions with DMUB using inbox1 and outbox1 mail boxes. [How] 1) Added inbox1 command DMUB_CMD__DP_AUX_ACCESS to issue AUX commands to DMUB in dc_process_dmub_aux_transfer_async(). DMUB processes AUX cmd with DCN and sends reply back in an outbox1 message triggering an outbox1 interrupt to driver. 2) In existing driver implementation, AUX commands are processed synchronously by configuring DCN reg. But in DMUB AUX, driver sends an inbox1 message and waits for a conditional variable (CV) which will be signaled by outbox1 ISR. 3) DM will retrieve Outbox1 message and send back reply to upper layer and complete the AUX command Signed-off-by: Jude Shih <shenshih@amd.com> Reviewed-by: Hanghong Ma <Hanghong.Ma@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Wayne Lin <Wayne.Lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c')
-rw-r--r--drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c13
1 files changed, 10 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index e8b325a828c1..90eacdac0ea0 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -640,7 +640,14 @@ enum dc_edid_status dm_helpers_read_local_edid(
return edid_status;
}
-
+int dm_helper_dmub_aux_transfer_sync(
+ struct dc_context *ctx,
+ const struct dc_link *link,
+ struct aux_payload *payload,
+ enum aux_return_code_type *operation_result)
+{
+ return amdgpu_dm_process_dmub_aux_transfer_sync(ctx, link->link_index, payload, operation_result);
+}
void dm_set_dcn_clocks(struct dc_context *ctx, struct dc_clocks *clks)
{
/* TODO: something */
@@ -698,12 +705,12 @@ void dm_helpers_free_gpu_mem(
}
}
-bool dm_helpers_dmub_outbox0_interrupt_control(struct dc_context *ctx, bool enable)
+bool dm_helpers_dmub_outbox_interrupt_control(struct dc_context *ctx, bool enable)
{
enum dc_irq_source irq_source;
bool ret;
- irq_source = DC_IRQ_SOURCE_DMCUB_OUTBOX0;
+ irq_source = DC_IRQ_SOURCE_DMCUB_OUTBOX;
ret = dc_interrupt_set(ctx->dc, irq_source, enable);