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| author | Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> | 2019-06-10 16:06:05 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-10-03 09:10:58 -0500 |
| commit | da3fd7ac0bcf372cc57117bdfcd725cca7ef975a (patch) | |
| tree | a3b6ad6d717b5c707b9a71ce448e4775a778c0c3 /drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h | |
| parent | 2a0f92700fe348fd5785f87e4730ab1c5398157a (diff) | |
| download | linux-da3fd7ac0bcf372cc57117bdfcd725cca7ef975a.tar.gz linux-da3fd7ac0bcf372cc57117bdfcd725cca7ef975a.tar.bz2 linux-da3fd7ac0bcf372cc57117bdfcd725cca7ef975a.zip | |
drm/amd/display: Update CP property based on HW query
[Why]
We need to use HW state to set content protection to ENABLED.
This way we know that the link is encrypted from the HW side
[How]
Create a workqueue that queries the HW every ~2seconds, and sets it to
ENABLED or DESIRED based on the result from the hardware
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h index cb6c6fbd74f6..d3ba505d0696 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h @@ -38,8 +38,11 @@ struct cp_psp; struct hdcp_workqueue { struct work_struct cpirq_work; + struct work_struct property_update_work; struct delayed_work callback_dwork; struct delayed_work watchdog_timer_dwork; + struct delayed_work property_validate_dwork; + struct amdgpu_dm_connector *aconnector; struct mutex mutex; struct mod_hdcp hdcp; @@ -47,10 +50,12 @@ struct hdcp_workqueue { struct mod_hdcp_display display; struct mod_hdcp_link link; + enum mod_hdcp_encryption_status encryption_status; uint8_t max_link; }; -void hdcp_add_display(struct hdcp_workqueue *hdcp_work, unsigned int link_index); +void hdcp_add_display(struct hdcp_workqueue *hdcp_work, unsigned int link_index, + struct amdgpu_dm_connector *aconnector); void hdcp_remove_display(struct hdcp_workqueue *work, unsigned int link_index, unsigned int display_index); void hdcp_reset_display(struct hdcp_workqueue *work, unsigned int link_index); void hdcp_handle_cpirq(struct hdcp_workqueue *work, unsigned int link_index); |