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| author | Marek Olšák <marek.olsak@amd.com> | 2021-02-04 02:46:20 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-02-18 16:42:55 -0500 |
| commit | 4112c00354004cbb1bf56f0114fa9951bf6b13ed (patch) | |
| tree | 4600616629e5826306e63ecacfebc3dbf998cdf4 /drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | |
| parent | a29d4b3d3caf91beba12187e4c78ec28e4a29c09 (diff) | |
| download | linux-4112c00354004cbb1bf56f0114fa9951bf6b13ed.tar.gz linux-4112c00354004cbb1bf56f0114fa9951bf6b13ed.tar.bz2 linux-4112c00354004cbb1bf56f0114fa9951bf6b13ed.zip | |
drm/amdgpu: fix CGTS_TCC_DISABLE register offset on gfx10.3
This fixes incorrect TCC harvesting info reported to userspace.
The impact was a very very tiny performance degradation (unnecessary
GL2 cache flushes).
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Diffstat (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c')
0 files changed, 0 insertions, 0 deletions