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| author | Aurabindo Pillai <aurabindo.pillai@amd.com> | 2023-08-04 11:07:59 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-08-30 14:58:29 -0400 |
| commit | 53d8e3beeaa92d916546abb4c4ac2b88d5a5b3f8 (patch) | |
| tree | 62e8e9b2b4ff4bbe2e3bd303efbb8dae65b5cc15 /drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | |
| parent | c183060031ee70b7641de260207b3013eebf5707 (diff) | |
| download | linux-53d8e3beeaa92d916546abb4c4ac2b88d5a5b3f8.tar.gz linux-53d8e3beeaa92d916546abb4c4ac2b88d5a5b3f8.tar.bz2 linux-53d8e3beeaa92d916546abb4c4ac2b88d5a5b3f8.zip | |
drm/amd/display: Expose mall capability
[Why&How]
Export a debugfs file to report whether MALL cache is supported by the
asic or not.
Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 7c21e21bcc51..b5f3b33b625d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -3606,6 +3606,23 @@ DEFINE_DEBUGFS_ATTRIBUTE(disable_hpd_ops, disable_hpd_get, disable_hpd_set, "%llu\n"); /* + * Returns 1 if hardware supports MALL cache + * 0 otherwise. + */ +static int capabilities_show(struct seq_file *m, void *unused) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)m->private; + struct dc_caps caps = adev->dm.dc->caps; + bool mall_supported = caps.mall_size_total; + + seq_printf(m, "mall: %s\n", mall_supported ? "yes" : "no"); + + return 0; +} + +DEFINE_SHOW_ATTRIBUTE(capabilities); + +/* * Temporary w/a to force sst sequence in M42D DP2 mst receiver * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_set_mst_en_for_sst */ @@ -3798,6 +3815,8 @@ void dtn_debugfs_init(struct amdgpu_device *adev) debugfs_create_file("amdgpu_mst_topology", 0444, root, adev, &mst_topo_fops); + debugfs_create_file("amdgpu_dm_capabilities", 0444, root, + adev, &capabilities_fops); debugfs_create_file("amdgpu_dm_dtn_log", 0644, root, adev, &dtn_log_fops); debugfs_create_file("amdgpu_dm_dp_set_mst_en_for_sst", 0644, root, adev, |