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| author | Dingchen Zhang <dingchen.zhang@amd.com> | 2019-06-28 17:23:24 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-07-18 14:27:25 -0500 |
| commit | f1cdc98fd9d9bb0eb4b6599825b52ce25757eb9f (patch) | |
| tree | 0a387c7bed846624b2906fb34f15b8210f0f540d /drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h | |
| parent | e9bcc1e03048b3872df46cc6ee28d5c43850e379 (diff) | |
| download | linux-f1cdc98fd9d9bb0eb4b6599825b52ce25757eb9f.tar.gz linux-f1cdc98fd9d9bb0eb4b6599825b52ce25757eb9f.tar.bz2 linux-f1cdc98fd9d9bb0eb4b6599825b52ce25757eb9f.zip | |
drm/amd/display: add pipe CRC sources without disabling dithering.
[Why]
need to verify the impact of spatial dithering on 8bpc bypass mode.
[How]
added CRC sources and configure dihter option from dc stream.
Signed-off-by: Dingchen Zhang <dingchen.zhang@amd.com>
Reviewed-by: Hanghong Ma <Hanghong.Ma@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h index b63a9011f511..14de7301c28d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h @@ -29,15 +29,17 @@ enum amdgpu_dm_pipe_crc_source { AMDGPU_DM_PIPE_CRC_SOURCE_NONE = 0, AMDGPU_DM_PIPE_CRC_SOURCE_CRTC, + AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER, AMDGPU_DM_PIPE_CRC_SOURCE_DPRX, + AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER, AMDGPU_DM_PIPE_CRC_SOURCE_MAX, AMDGPU_DM_PIPE_CRC_SOURCE_INVALID = -1, }; static inline bool amdgpu_dm_is_valid_crc_source(enum amdgpu_dm_pipe_crc_source source) { - return (source == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC) || - (source == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX); + return (source > AMDGPU_DM_PIPE_CRC_SOURCE_NONE) && + (source < AMDGPU_DM_PIPE_CRC_SOURCE_MAX); } /* amdgpu_dm_crc.c */ |