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authorYifan Zha <Yifan.Zha@amd.com>2022-08-19 11:02:19 +0800
committerAlex Deucher <alexander.deucher@amd.com>2022-09-01 15:11:54 -0400
commit828418259254863e0af5805bd712284e2bd88e3b (patch)
treeb50fd4834a034e8b2a0dfecc806237e64dceda60 /drivers/gpu/drm/amd/amdgpu/soc21.c
parentbbb860d46fcbde5881c93ed549445a85f2434a64 (diff)
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drm/admgpu: Skip CG/PG on SOC21 under SRIOV VF
[Why] There is no CG(Clock Gating)/PG(Power Gating) requirement on SRIOV VF. For multi VF, VF should not enable any CG/PG features. For one VF, PF will program CG/PG related registers. [How] Do not set any cg/pg flag bit at early init under sriov. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Yifan Zha <Yifan.Zha@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/soc21.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/soc21.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c
index 47ef671543b3..34a267265971 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -582,6 +582,10 @@ static int soc21_common_early_init(void *handle)
AMD_PG_SUPPORT_JPEG |
AMD_PG_SUPPORT_ATHUB |
AMD_PG_SUPPORT_MMHUB;
+ if (amdgpu_sriov_vf(adev)) {
+ adev->cg_flags = 0;
+ adev->pg_flags = 0;
+ }
adev->external_rev_id = adev->rev_id + 0x1; // TODO: need update
break;
case IP_VERSION(11, 0, 2):