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| author | Leo Liu <leo.liu@amd.com> | 2019-05-13 12:15:45 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-05-24 12:20:52 -0500 |
| commit | 05eee12dd60ed5f19fefa93a79bacad9dd2c5883 (patch) | |
| tree | 297e05c6a69f89ac371050ae289757cdfd070521 /drivers/gpu/drm/amd/amdgpu/soc15_common.h | |
| parent | fe2b5323d2c3cedaa3bf943dc7a0d233c853c914 (diff) | |
| download | linux-05eee12dd60ed5f19fefa93a79bacad9dd2c5883.tar.gz linux-05eee12dd60ed5f19fefa93a79bacad9dd2c5883.tar.bz2 linux-05eee12dd60ed5f19fefa93a79bacad9dd2c5883.zip | |
drm/amdgpu: move the VCN DPG mode read and write to VCN
Since this is VCN specific and only used by VCN
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/soc15_common.h')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/soc15_common.h | 21 |
1 files changed, 0 insertions, 21 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h b/drivers/gpu/drm/amd/amdgpu/soc15_common.h index c634606e64bd..47f74dab365d 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h +++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h @@ -69,27 +69,6 @@ } \ } while (0) -#define RREG32_SOC15_DPG_MODE(ip, inst, reg, mask, sram_sel) \ - ({ WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask); \ - WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL, \ - UVD_DPG_LMA_CTL__MASK_EN_MASK | \ - ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \ - << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | \ - (sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \ - RREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA); }) - -#define WREG32_SOC15_DPG_MODE(ip, inst, reg, value, mask, sram_sel) \ - do { \ - WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA, value); \ - WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask); \ - WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL, \ - UVD_DPG_LMA_CTL__READ_WRITE_MASK | \ - ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \ - << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | \ - (sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \ - } while (0) - - #define WREG32_RLC(reg, value) \ do { \ if (amdgpu_virt_support_rlc_prg_reg(adev)) { \ |