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| author | Alex Deucher <alexander.deucher@amd.com> | 2017-12-08 11:39:49 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-12-12 14:50:17 -0500 |
| commit | 74e1d67c73b93634ce2436c10688a7cfea68678e (patch) | |
| tree | 82a17143343b16f1cc84de7d0ddd1f7111a53421 /drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c | |
| parent | 1cb4ca59687dc941d5df56aa63ff9c7fa7f7e92f (diff) | |
| download | linux-74e1d67c73b93634ce2436c10688a7cfea68678e.tar.gz linux-74e1d67c73b93634ce2436c10688a7cfea68678e.tar.bz2 linux-74e1d67c73b93634ce2436c10688a7cfea68678e.zip | |
drm/amdgpu: make function names consistent in nbio files
All functions should have nbio_v* prefix.
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c index ce869f37a382..851f58e0b9d9 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c @@ -182,22 +182,22 @@ void nbio_v7_0_ih_control(struct amdgpu_device *adev) WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl); } -static u32 get_hdp_flush_req_offset(struct amdgpu_device *adev) +static u32 nbio_v7_0_get_hdp_flush_req_offset(struct amdgpu_device *adev) { return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ); } -static u32 get_hdp_flush_done_offset(struct amdgpu_device *adev) +static u32 nbio_v7_0_get_hdp_flush_done_offset(struct amdgpu_device *adev) { return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE); } -static u32 get_pcie_index_offset(struct amdgpu_device *adev) +static u32 nbio_v7_0_get_pcie_index_offset(struct amdgpu_device *adev) { return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2); } -static u32 get_pcie_data_offset(struct amdgpu_device *adev) +static u32 nbio_v7_0_get_pcie_data_offset(struct amdgpu_device *adev) { return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2); } @@ -218,9 +218,9 @@ const struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg = { }; const struct amdgpu_nbio_funcs nbio_v7_0_funcs = { - .get_hdp_flush_req_offset = get_hdp_flush_req_offset, - .get_hdp_flush_done_offset = get_hdp_flush_done_offset, - .get_pcie_index_offset = get_pcie_index_offset, - .get_pcie_data_offset = get_pcie_data_offset, + .get_hdp_flush_req_offset = nbio_v7_0_get_hdp_flush_req_offset, + .get_hdp_flush_done_offset = nbio_v7_0_get_hdp_flush_done_offset, + .get_pcie_index_offset = nbio_v7_0_get_pcie_index_offset, + .get_pcie_data_offset = nbio_v7_0_get_pcie_data_offset, }; |