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| author | Yifan Zhang <yifan1.zhang@amd.com> | 2024-05-06 15:48:54 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2024-06-05 11:02:30 -0400 |
| commit | b7e2170b87938f8a4664018111de3ba8c1ed2db3 (patch) | |
| tree | c9d5c3ba2590ac6c4307383cfbe3a320e5ee6c12 /drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c | |
| parent | 98f9e5ea474d834eed2e1fb163ef3ab956ef8205 (diff) | |
| download | linux-b7e2170b87938f8a4664018111de3ba8c1ed2db3.tar.gz linux-b7e2170b87938f8a4664018111de3ba8c1ed2db3.tar.bz2 linux-b7e2170b87938f8a4664018111de3ba8c1ed2db3.zip | |
drm/amdgpu: init SAW registers for mmhub v3.3
This patch to configure mmhub3.3 SAW registers
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c index 238ea40c2450..b22751a25c9c 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c @@ -359,6 +359,43 @@ static void mmhub_v3_3_program_invalidation(struct amdgpu_device *adev) } } +static void mmhub_v3_3_init_saw_regs(struct amdgpu_device *adev) +{ + uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); + uint32_t tmp; + + /* Program page table base, gart start, gart end */ + WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, + lower_32_bits(pt_base >> 12)); + WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, + upper_32_bits(pt_base >> 12)); + + WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, + (u32)(adev->gmc.gart_start >> 12)); + WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, + (u32)(adev->gmc.gart_start >> 44)); + + WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, + (u32)(adev->gmc.gart_end >> 12)); + WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, + (u32)(adev->gmc.gart_end >> 44)); + + tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXT0_CNTL); + tmp = REG_SET_FIELD(tmp, MMVM_L2_SAW_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); + tmp = REG_SET_FIELD(tmp, MMVM_L2_SAW_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); + WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXT0_CNTL, tmp); + + /* Disable all contexts except context 0 */ + tmp = 0xfffe; + WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CONTEXTS_DISABLE, tmp); + + /* Program saw cntl4 */ + tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CNTL4); + tmp = REG_SET_FIELD(tmp, MMVM_L2_SAW_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 1); + tmp = REG_SET_FIELD(tmp, MMVM_L2_SAW_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 1); + WREG32_SOC15(MMHUB, 0, regMMVM_L2_SAW_CNTL4, tmp); +} + static int mmhub_v3_3_gart_enable(struct amdgpu_device *adev) { /* GART Enable. */ @@ -372,6 +409,9 @@ static int mmhub_v3_3_gart_enable(struct amdgpu_device *adev) mmhub_v3_3_setup_vmid_config(adev); mmhub_v3_3_program_invalidation(adev); + /* standalone alone walker init */ + mmhub_v3_3_init_saw_regs(adev); + return 0; } |