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| author | Victor Lu <victorchengchi.lu@amd.com> | 2023-06-16 11:01:59 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-07-18 11:16:41 -0400 |
| commit | 8ed49dd1d3a7448744d57e1da2062b074cba2e49 (patch) | |
| tree | 853c08a5a0e155d70a6b67c9d6561d9d66e07b9b /drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h | |
| parent | 4a8e0f9558d74053a5f23bd02dff6883dc837aaf (diff) | |
| download | linux-8ed49dd1d3a7448744d57e1da2062b074cba2e49.tar.gz linux-8ed49dd1d3a7448744d57e1da2062b074cba2e49.tar.bz2 linux-8ed49dd1d3a7448744d57e1da2062b074cba2e49.zip | |
drm/amdgpu: Add RLCG interface driver implementation for gfx v9.4.3 (v3)
Add RLCG interface support for gfx v9.4.3 and multiple XCCs.
Do not enable it yet.
v2: Fix amdgpu_rlcg_reg_access_ctrl init, add support for multiple XCCs
in amdgpu_mm_wreg_mmio_rlc
v3: Use GET_INST() when indexing amdgpu_rlcg_reg_access_ctrl
Signed-off-by: Victor Lu <victorchengchi.lu@amd.com>
Reviewed-by: Zhigang Luo <zhigang.luo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h index 80b263646966..b591d33af264 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h @@ -26,6 +26,8 @@ #include "clearstate_defs.h" +#define AMDGPU_MAX_RLC_INSTANCES 8 + /* firmware ID used in rlc toc */ typedef enum _FIRMWARE_ID_ { FIRMWARE_ID_INVALID = 0, @@ -201,7 +203,7 @@ struct amdgpu_rlc { u32 cp_table_size; /* safe mode for updating CG/PG state */ - bool in_safe_mode[8]; + bool in_safe_mode[AMDGPU_MAX_RLC_INSTANCES]; const struct amdgpu_rlc_funcs *funcs; /* for firmware data */ @@ -257,7 +259,7 @@ struct amdgpu_rlc { bool rlcg_reg_access_supported; /* registers for rlcg indirect reg access */ - struct amdgpu_rlcg_reg_access_ctrl reg_access_ctrl; + struct amdgpu_rlcg_reg_access_ctrl reg_access_ctrl[AMDGPU_MAX_RLC_INSTANCES]; }; void amdgpu_gfx_rlc_enter_safe_mode(struct amdgpu_device *adev, int xcc_id); |