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| author | Ken Wang <Ken.Wang@amd.com> | 2017-07-04 13:11:52 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-07-14 11:06:06 -0400 |
| commit | 47ed4e1c93a6c73f313022369c12ddd693890715 (patch) | |
| tree | 3e822ce6750a35088368b8134a15353a82dc01c2 /drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | |
| parent | 4426826c02dc367ec3c245ef5c5ca4dcdb45b4c8 (diff) | |
| download | linux-47ed4e1c93a6c73f313022369c12ddd693890715.tar.gz linux-47ed4e1c93a6c73f313022369c12ddd693890715.tar.bz2 linux-47ed4e1c93a6c73f313022369c12ddd693890715.zip | |
drm/amdgpu: add workaround for S3 issues on some vega10 boards
Certain MC registers need a delay after writing them to properly
update in the init sequence.
Signed-off-by: Ken Wang <Ken.Wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c')
0 files changed, 0 insertions, 0 deletions