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| author | Doug Brown <doug@schmorgal.com> | 2022-06-12 12:29:28 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2022-09-30 13:34:06 -0700 |
| commit | 260d2f347b765422584a5fa5209b8ecd17d773b4 (patch) | |
| tree | cb10ee4007fd9235c7fcdec2e652b3f6762788e4 /drivers/clk/meson/clk-phase.h | |
| parent | a77a1e2f1b00ec3385523283b8fcbd56ed166797 (diff) | |
| download | linux-260d2f347b765422584a5fa5209b8ecd17d773b4.tar.gz linux-260d2f347b765422584a5fa5209b8ecd17d773b4.tar.bz2 linux-260d2f347b765422584a5fa5209b8ecd17d773b4.zip | |
dt-bindings: marvell,pxa168: add clock ids for additional dividers
This adds a few new clocks divided from PLL1 and CLK32 that are
potentially used by a few peripherals with muxed clocks.
Signed-off-by: Doug Brown <doug@schmorgal.com>
Link: https://lore.kernel.org/r/20220612192937.162952-4-doug@schmorgal.com
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/meson/clk-phase.h')
0 files changed, 0 insertions, 0 deletions