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| author | Lai Jiangshan <laijs@linux.alibaba.com> | 2021-09-19 10:42:46 +0800 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2021-10-22 05:19:29 -0400 |
| commit | a91a7c7096005113d8e749fd8dfdd3e1eecee263 (patch) | |
| tree | fc845ad074a0eb01ad296a91e1cd8869ce1c8df0 /arch/x86/kvm/mmu.h | |
| parent | 552617382c197949ff965a3559da8952bf3c1fa5 (diff) | |
| download | linux-a91a7c7096005113d8e749fd8dfdd3e1eecee263.tar.gz linux-a91a7c7096005113d8e749fd8dfdd3e1eecee263.tar.bz2 linux-a91a7c7096005113d8e749fd8dfdd3e1eecee263.zip | |
KVM: X86: Don't reset mmu context when toggling X86_CR4_PGE
X86_CR4_PGE doesn't participate in kvm_mmu_role, so the mmu context
doesn't need to be reset. It is only required to flush all the guest
tlb.
It is also inconsistent that X86_CR4_PGE is in KVM_MMU_CR4_ROLE_BITS
while kvm_mmu_role doesn't use X86_CR4_PGE. So X86_CR4_PGE is also
removed from KVM_MMU_CR4_ROLE_BITS.
Signed-off-by: Lai Jiangshan <laijs@linux.alibaba.com>
Reviewed-by: Sean Christopherson <seanjc@google.com>
Message-Id: <20210919024246.89230-3-jiangshanlai@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'arch/x86/kvm/mmu.h')
| -rw-r--r-- | arch/x86/kvm/mmu.h | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/arch/x86/kvm/mmu.h b/arch/x86/kvm/mmu.h index c921619f7dc9..3456f4d0eaeb 100644 --- a/arch/x86/kvm/mmu.h +++ b/arch/x86/kvm/mmu.h @@ -44,9 +44,8 @@ #define PT32_ROOT_LEVEL 2 #define PT32E_ROOT_LEVEL 3 -#define KVM_MMU_CR4_ROLE_BITS (X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | \ - X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE | \ - X86_CR4_LA57) +#define KVM_MMU_CR4_ROLE_BITS (X86_CR4_PSE | X86_CR4_PAE | X86_CR4_LA57 | \ + X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE) #define KVM_MMU_CR0_ROLE_BITS (X86_CR0_PG | X86_CR0_WP) |