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| author | Ricardo Cañuelo <ricardo.canuelo@collabora.com> | 2022-04-01 09:45:17 +0200 |
|---|---|---|
| committer | Borislav Petkov <bp@suse.de> | 2022-04-05 21:55:57 +0200 |
| commit | 0205f8a738ab9e62d849e88e543cfa6ce4c13163 (patch) | |
| tree | 3bd3ddea3f0c019a939ab5b97f8bcd170ec75a9a /arch/x86/kernel/cpu/bugs.c | |
| parent | f8858b5eff30d1b2be15ef1ea6285964013b95e6 (diff) | |
| download | linux-0205f8a738ab9e62d849e88e543cfa6ce4c13163.tar.gz linux-0205f8a738ab9e62d849e88e543cfa6ce4c13163.tar.bz2 linux-0205f8a738ab9e62d849e88e543cfa6ce4c13163.zip | |
x86/speculation/srbds: Do not try to turn mitigation off when not supported
When SRBDS is mitigated by TSX OFF, update_srbds_msr() will still read
and write to MSR_IA32_MCU_OPT_CTRL even when that MSR is not supported
due to not having loaded the appropriate microcode.
Check for X86_FEATURE_SRBDS_CTRL which is set only when the respective
microcode which adds MSR_IA32_MCU_OPT_CTRL is loaded.
Based on a patch by Thadeu Lima de Souza Cascardo <cascardo@canonical.com>.
[ bp: Massage commit message. ]
Suggested-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Signed-off-by: Ricardo Cañuelo <ricardo.canuelo@collabora.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: https://lore.kernel.org/r/20220401074517.1848264-1-ricardo.canuelo@collabora.com
Diffstat (limited to 'arch/x86/kernel/cpu/bugs.c')
| -rw-r--r-- | arch/x86/kernel/cpu/bugs.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 6296e1ebed1d..d879a6c93609 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -446,6 +446,13 @@ void update_srbds_msr(void) if (srbds_mitigation == SRBDS_MITIGATION_UCODE_NEEDED) return; + /* + * A MDS_NO CPU for which SRBDS mitigation is not needed due to TSX + * being disabled and it hasn't received the SRBDS MSR microcode. + */ + if (!boot_cpu_has(X86_FEATURE_SRBDS_CTRL)) + return; + rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl); switch (srbds_mitigation) { |