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| author | Tiwei Bie <tiwei.btw@antgroup.com> | 2024-09-18 14:17:02 +0800 |
|---|---|---|
| committer | Johannes Berg <johannes.berg@intel.com> | 2024-10-10 12:06:43 +0200 |
| commit | ed236fe4daf770ae10d6146bde0b00c39618a557 (patch) | |
| tree | 52221084ed349febe2f365b15e9391c26896f027 /arch/um/include/asm/pgtable-3level.h | |
| parent | 5a6951273e0e9dc0f79facf22281a8a731fb90b1 (diff) | |
| download | linux-ed236fe4daf770ae10d6146bde0b00c39618a557.tar.gz linux-ed236fe4daf770ae10d6146bde0b00c39618a557.tar.bz2 linux-ed236fe4daf770ae10d6146bde0b00c39618a557.zip | |
um: Remove 3-level page table support on i386
The highmem support has been removed by commit a98a6d864d3b ("um:
Remove broken highmem support"). The 2-level page table is sufficient
on UML/i386 now. Remove the 3-level page table support on UML/i386
which is still marked as experimental.
Suggested-by: Benjamin Berg <benjamin@sipsolutions.net>
Signed-off-by: Tiwei Bie <tiwei.btw@antgroup.com>
Link: https://patch.msgid.link/20240918061702.614837-1-tiwei.btw@antgroup.com
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
Diffstat (limited to 'arch/um/include/asm/pgtable-3level.h')
| -rw-r--r-- | arch/um/include/asm/pgtable-3level.h | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/arch/um/include/asm/pgtable-3level.h b/arch/um/include/asm/pgtable-3level.h index 8a5032ec231f..3504a92dc485 100644 --- a/arch/um/include/asm/pgtable-3level.h +++ b/arch/um/include/asm/pgtable-3level.h @@ -11,11 +11,7 @@ /* PGDIR_SHIFT determines what a third-level page table entry can map */ -#ifdef CONFIG_64BIT #define PGDIR_SHIFT 30 -#else -#define PGDIR_SHIFT 31 -#endif #define PGDIR_SIZE (1UL << PGDIR_SHIFT) #define PGDIR_MASK (~(PGDIR_SIZE-1)) @@ -32,13 +28,8 @@ */ #define PTRS_PER_PTE 512 -#ifdef CONFIG_64BIT #define PTRS_PER_PMD 512 #define PTRS_PER_PGD 512 -#else -#define PTRS_PER_PMD 1024 -#define PTRS_PER_PGD 1024 -#endif #define USER_PTRS_PER_PGD ((TASK_SIZE + (PGDIR_SIZE - 1)) / PGDIR_SIZE) |