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| author | WANG Xuerui <git@xen0n.name> | 2020-07-29 21:14:16 +0800 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2020-07-31 17:52:29 +0200 |
| commit | 2480c914699ecdf8b560f7af23b1a9c521084e04 (patch) | |
| tree | 73e23afb9bca97563ec9d0679fa5d79bd108c772 /arch/mips/kernel/traps.c | |
| parent | efd1b4ad3d5178a74387bc5ff69a2d4585f586c6 (diff) | |
| download | linux-2480c914699ecdf8b560f7af23b1a9c521084e04.tar.gz linux-2480c914699ecdf8b560f7af23b1a9c521084e04.tar.bz2 linux-2480c914699ecdf8b560f7af23b1a9c521084e04.zip | |
MIPS: add definitions for Loongson-specific CP0.Diag1 register
This 32-bit CP0 register is named GSCause in Loongson manuals. It carries
Loongson extended exception information. We name it Diag1 because we
fear the "GSCause" name might get changed in the future.
Reviewed-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: WANG Xuerui <git@xen0n.name>
Cc: Huacai Chen <chenhc@lemote.com>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Tiezhu Yang <yangtiezhu@loongson.cn>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/kernel/traps.c')
0 files changed, 0 insertions, 0 deletions