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| author | Claudiu Beznea <claudiu.beznea@microchip.com> | 2021-09-15 10:48:35 +0300 |
|---|---|---|
| committer | Nicolas Ferre <nicolas.ferre@microchip.com> | 2021-10-04 12:16:58 +0200 |
| commit | 968f6e9d51e2da6eade2afb65629ab87a8a0faf3 (patch) | |
| tree | a261e9e8fba30d6878c5e744c9b9171f5b7dfdc3 /arch/m68k/kernel | |
| parent | d8d667ee0236dec6d717f27eec690d1324e7f322 (diff) | |
| download | linux-968f6e9d51e2da6eade2afb65629ab87a8a0faf3.tar.gz linux-968f6e9d51e2da6eade2afb65629ab87a8a0faf3.tar.bz2 linux-968f6e9d51e2da6eade2afb65629ab87a8a0faf3.zip | |
ARM: dts: at91: sama7g5ek: use proper slew-rate settings for GMACs
Datasheet chapter "EMAC Timings" specifies that while in 3.3V domain
GMAC's MDIO pins should be configured with slew-rate enabled, while the
data + signaling pins should be configured with slew-rate disabled when
GMAC works in RGMII or RMII modes. The pin controller for SAMA7G5 sets
the slew-rate as enabled for all pins. Adapt the device tree to comply
with these.
Fixes: 7540629e2fc7 ("ARM: dts: at91: add sama7g5 SoC DT and sama7g5-ek")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20210915074836.6574-2-claudiu.beznea@microchip.com
Diffstat (limited to 'arch/m68k/kernel')
0 files changed, 0 insertions, 0 deletions