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| author | Arnd Bergmann <arnd@arndb.de> | 2018-03-07 21:36:19 +0100 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2018-03-09 23:20:00 +0100 |
| commit | 553b085c2075f6a4a2591108554f830fa61e881f (patch) | |
| tree | 68d63911f2c12e0fb9fa23498df9300442a88f92 /arch/m32r/include/asm/irq.h | |
| parent | fd8773f9f544955f6f47dc2ac3ab85ad64376b7f (diff) | |
| download | linux-553b085c2075f6a4a2591108554f830fa61e881f.tar.gz linux-553b085c2075f6a4a2591108554f830fa61e881f.tar.bz2 linux-553b085c2075f6a4a2591108554f830fa61e881f.zip | |
arch: remove m32r port
The Mitsubishi/Renesas m32r architecture has been around for many years,
but the Linux port has been obsolete for a very long time as well, with
the last significant updates done for linux-2.6.14.
While some m32r microcontrollers are still being marketed by Renesas,
those are apparently no longer possible to support, mainly due to the
lack of an external memory interface.
Hirokazu Takata was the maintainer until the architecture got marked
Orphaned in 2014.
Link: http://www.linux-m32r.org/
Link: https://www.renesas.com/en-eu/products/microcontrollers-microprocessors/m32r.html
Cc: Hirokazu Takata <takata@linux-m32r.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/m32r/include/asm/irq.h')
| -rw-r--r-- | arch/m32r/include/asm/irq.h | 91 |
1 files changed, 0 insertions, 91 deletions
diff --git a/arch/m32r/include/asm/irq.h b/arch/m32r/include/asm/irq.h deleted file mode 100644 index 85b475fff90e..000000000000 --- a/arch/m32r/include/asm/irq.h +++ /dev/null @@ -1,91 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifdef __KERNEL__ -#ifndef _ASM_M32R_IRQ_H -#define _ASM_M32R_IRQ_H - - -#if defined(CONFIG_PLAT_USRV) -/* - * IRQ definitions for M32700UT - * M32700 Chip: 64 interrupts - * ICU of M32700UT-on-board PLD: 32 interrupts cascaded to INT1# chip pin - */ -#define M32700UT_NUM_CPU_IRQ (64) -#define M32700UT_NUM_PLD_IRQ (32) -#define M32700UT_IRQ_BASE 0 -#define M32700UT_CPU_IRQ_BASE M32700UT_IRQ_BASE -#define M32700UT_PLD_IRQ_BASE (M32700UT_CPU_IRQ_BASE + M32700UT_NUM_CPU_IRQ) - -#define NR_IRQS (M32700UT_NUM_CPU_IRQ + M32700UT_NUM_PLD_IRQ) -#elif defined(CONFIG_PLAT_M32700UT) -/* - * IRQ definitions for M32700UT(Rev.C) + M32R-LAN - * M32700 Chip: 64 interrupts - * ICU of M32700UT-on-board PLD: 32 interrupts cascaded to INT1# chip pin - * ICU of M32R-LCD-on-board PLD: 32 interrupts cascaded to INT2# chip pin - * ICU of M32R-LAN-on-board PLD: 32 interrupts cascaded to INT0# chip pin - */ -#define M32700UT_NUM_CPU_IRQ (64) -#define M32700UT_NUM_PLD_IRQ (32) -#define M32700UT_NUM_LCD_PLD_IRQ (32) -#define M32700UT_NUM_LAN_PLD_IRQ (32) -#define M32700UT_IRQ_BASE 0 -#define M32700UT_CPU_IRQ_BASE (M32700UT_IRQ_BASE) -#define M32700UT_PLD_IRQ_BASE \ - (M32700UT_CPU_IRQ_BASE + M32700UT_NUM_CPU_IRQ) -#define M32700UT_LCD_PLD_IRQ_BASE \ - (M32700UT_PLD_IRQ_BASE + M32700UT_NUM_PLD_IRQ) -#define M32700UT_LAN_PLD_IRQ_BASE \ - (M32700UT_LCD_PLD_IRQ_BASE + M32700UT_NUM_LCD_PLD_IRQ) - -#define NR_IRQS \ - (M32700UT_NUM_CPU_IRQ + M32700UT_NUM_PLD_IRQ \ - + M32700UT_NUM_LCD_PLD_IRQ + M32700UT_NUM_LAN_PLD_IRQ) -#elif defined(CONFIG_PLAT_OPSPUT) -/* - * IRQ definitions for OPSPUT + M32R-LAN - * OPSP Chip: 64 interrupts - * ICU of OPSPUT-on-board PLD: 32 interrupts cascaded to INT1# chip pin - * ICU of M32R-LCD-on-board PLD: 32 interrupts cascaded to INT2# chip pin - * ICU of M32R-LAN-on-board PLD: 32 interrupts cascaded to INT0# chip pin - */ -#define OPSPUT_NUM_CPU_IRQ (64) -#define OPSPUT_NUM_PLD_IRQ (32) -#define OPSPUT_NUM_LCD_PLD_IRQ (32) -#define OPSPUT_NUM_LAN_PLD_IRQ (32) -#define OPSPUT_IRQ_BASE 0 -#define OPSPUT_CPU_IRQ_BASE (OPSPUT_IRQ_BASE) -#define OPSPUT_PLD_IRQ_BASE \ - (OPSPUT_CPU_IRQ_BASE + OPSPUT_NUM_CPU_IRQ) -#define OPSPUT_LCD_PLD_IRQ_BASE \ - (OPSPUT_PLD_IRQ_BASE + OPSPUT_NUM_PLD_IRQ) -#define OPSPUT_LAN_PLD_IRQ_BASE \ - (OPSPUT_LCD_PLD_IRQ_BASE + OPSPUT_NUM_LCD_PLD_IRQ) - -#define NR_IRQS \ - (OPSPUT_NUM_CPU_IRQ + OPSPUT_NUM_PLD_IRQ \ - + OPSPUT_NUM_LCD_PLD_IRQ + OPSPUT_NUM_LAN_PLD_IRQ) - -#elif defined(CONFIG_PLAT_M32104UT) -/* - * IRQ definitions for M32104UT - * M32104 Chip: 64 interrupts - * ICU of M32104UT-on-board PLD: 32 interrupts cascaded to INT1# chip pin - */ -#define M32104UT_NUM_CPU_IRQ (64) -#define M32104UT_NUM_PLD_IRQ (32) -#define M32104UT_IRQ_BASE 0 -#define M32104UT_CPU_IRQ_BASE M32104UT_IRQ_BASE -#define M32104UT_PLD_IRQ_BASE (M32104UT_CPU_IRQ_BASE + M32104UT_NUM_CPU_IRQ) - -#define NR_IRQS \ - (M32104UT_NUM_CPU_IRQ + M32104UT_NUM_PLD_IRQ) - -#else -#define NR_IRQS 64 -#endif - -#define irq_canonicalize(irq) (irq) - -#endif /* _ASM_M32R_IRQ_H */ -#endif /* __KERNEL__ */ |