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| author | Will Deacon <will@kernel.org> | 2022-03-14 19:04:22 +0000 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2022-03-14 19:04:22 +0000 |
| commit | 8d93b7a242b2adf36949c10b8eb9cc084a74b59a (patch) | |
| tree | dc6a45f281eb89c5b35ceef5698400b9ee11b237 /arch/arm64/include/asm/sysreg.h | |
| parent | 515e5da7b6b52c5d6c7a54fe34165b86361041b5 (diff) | |
| parent | f2c281204b47309534f26dc63cee2a130c2b497b (diff) | |
| download | linux-8d93b7a242b2adf36949c10b8eb9cc084a74b59a.tar.gz linux-8d93b7a242b2adf36949c10b8eb9cc084a74b59a.tar.bz2 linux-8d93b7a242b2adf36949c10b8eb9cc084a74b59a.zip | |
Merge branch 'for-next/fpsimd' into for-next/core
* for-next/fpsimd:
arm64: cpufeature: Warn if we attempt to read a zero width field
arm64: cpufeature: Add missing .field_width for GIC system registers
arm64: signal: nofpsimd: Do not allocate fp/simd context when not available
arm64: cpufeature: Always specify and use a field width for capabilities
arm64: Always use individual bits in CPACR floating point enables
arm64: Define CPACR_EL1_FPEN similarly to other floating point controls
Diffstat (limited to 'arch/arm64/include/asm/sysreg.h')
| -rw-r--r-- | arch/arm64/include/asm/sysreg.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 89b58b73a8c1..2023a0e6c6d6 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -1109,9 +1109,11 @@ #define ZCR_ELx_LEN_SIZE 9 #define ZCR_ELx_LEN_MASK 0x1ff +#define CPACR_EL1_FPEN_EL1EN (BIT(20)) /* enable EL1 access */ +#define CPACR_EL1_FPEN_EL0EN (BIT(21)) /* enable EL0 access, if EL1EN set */ + #define CPACR_EL1_ZEN_EL1EN (BIT(16)) /* enable EL1 access */ #define CPACR_EL1_ZEN_EL0EN (BIT(17)) /* enable EL0 access, if EL1EN set */ -#define CPACR_EL1_ZEN (CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN) /* GCR_EL1 Definitions */ #define SYS_GCR_EL1_RRND (BIT(16)) |