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| author | Boris Brezillon <boris.brezillon@free-electrons.com> | 2015-11-11 22:30:30 +0100 |
|---|---|---|
| committer | Boris Brezillon <boris.brezillon@free-electrons.com> | 2016-04-19 22:05:38 +0200 |
| commit | 5abcd95d8c69008c72d54d7763e0ee2b5df84ac4 (patch) | |
| tree | 5eb62927cb19084d9b14071a54c2b24e55736634 | |
| parent | 2d43457f79e48ee427666fdbfe9a53f35d3a1672 (diff) | |
| download | linux-5abcd95d8c69008c72d54d7763e0ee2b5df84ac4.tar.gz linux-5abcd95d8c69008c72d54d7763e0ee2b5df84ac4.tar.bz2 linux-5abcd95d8c69008c72d54d7763e0ee2b5df84ac4.zip | |
mtd: nand: sunxi: adapt clk_rate to tWB, tADL, tWHR and tRHW timings
Adapt the NAND controller clk rate to the tWB, tADL, tWHR and tRHW
timings instead of returning an error when the maximum clk divisor is
not big enough to provide an appropriate timing.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| -rw-r--r-- | drivers/mtd/nand/sunxi_nand.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/mtd/nand/sunxi_nand.c b/drivers/mtd/nand/sunxi_nand.c index b906fc5a22fe..e30276d9a9e3 100644 --- a/drivers/mtd/nand/sunxi_nand.c +++ b/drivers/mtd/nand/sunxi_nand.c @@ -1163,6 +1163,18 @@ static int sunxi_nand_chip_set_timings(struct sunxi_nand_chip *chip, min_clk_period = DIV_ROUND_UP(timings->tWC_min, 2); /* T16 - T19 + tCAD */ + if (timings->tWB_max > (min_clk_period * 20)) + min_clk_period = DIV_ROUND_UP(timings->tWB_max, 20); + + if (timings->tADL_min > (min_clk_period * 32)) + min_clk_period = DIV_ROUND_UP(timings->tADL_min, 32); + + if (timings->tWHR_min > (min_clk_period * 32)) + min_clk_period = DIV_ROUND_UP(timings->tWHR_min, 32); + + if (timings->tRHW_min > (min_clk_period * 20)) + min_clk_period = DIV_ROUND_UP(timings->tRHW_min, 20); + tWB = sunxi_nand_lookup_timing(tWB_lut, timings->tWB_max, min_clk_period); if (tWB < 0) { |