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| author | Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> | 2024-04-16 11:24:05 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2024-04-30 09:54:16 -0400 |
| commit | 47745acc5e8dd9b92dc877d3436801106c5e6864 (patch) | |
| tree | 71f9e847975589b5a8d4907eb28326e3a0d0d7ba | |
| parent | 9ba971b25316b7e3a11b63b770a3a48bf3b69904 (diff) | |
| download | linux-47745acc5e8dd9b92dc877d3436801106c5e6864.tar.gz linux-47745acc5e8dd9b92dc877d3436801106c5e6864.tar.bz2 linux-47745acc5e8dd9b92dc877d3436801106c5e6864.zip | |
drm/amd/display: Add trigger FIFO resync path for DCN35
[Why]
FIFO error can occur if we don't trigger a DISPCLK change after
touching K1/K2 dividers. For 4k144 eDP + hotplug of USB-C DP display
we see FIFO underflow.
[How]
We have the path to trigger the resync as the workaround in
DCN314/DCN32, it just needs to be ported over to DCN35.
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c | 10 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c | 2 |
2 files changed, 12 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c index 4c53e339e325..4b282b7e0996 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c @@ -41,6 +41,15 @@ #define DC_LOGGER \ dccg->ctx->logger +static void dccg35_trigger_dio_fifo_resync(struct dccg *dccg) +{ + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + uint32_t dispclk_rdivider_value = 0; + + REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_RDIVIDER, &dispclk_rdivider_value); + REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, dispclk_rdivider_value); +} + static void dcn35_set_dppclk_enable(struct dccg *dccg, uint32_t dpp_inst, uint32_t enable) { @@ -1056,6 +1065,7 @@ static const struct dccg_funcs dccg35_funcs = { .enable_dsc = dccg35_enable_dscclk, .set_pixel_rate_div = dccg35_set_pixel_rate_div, .get_pixel_rate_div = dccg35_get_pixel_rate_div, + .trigger_dio_fifo_resync = dccg35_trigger_dio_fifo_resync, .set_valid_pixel_rate = dccg35_set_valid_pixel_rate, .enable_symclk_se = dccg35_enable_symclk_se, .disable_symclk_se = dccg35_disable_symclk_se, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c index 7ed5de5c5ec1..0e87f3503265 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c @@ -31,6 +31,7 @@ #include "dcn30/dcn30_hwseq.h" #include "dcn301/dcn301_hwseq.h" #include "dcn31/dcn31_hwseq.h" +#include "dcn314/dcn314_hwseq.h" #include "dcn32/dcn32_hwseq.h" #include "dcn35/dcn35_hwseq.h" @@ -158,6 +159,7 @@ static const struct hwseq_private_funcs dcn35_private_funcs = { .setup_hpo_hw_control = dcn35_setup_hpo_hw_control, .calculate_dccg_k1_k2_values = dcn32_calculate_dccg_k1_k2_values, .set_pixels_per_cycle = dcn32_set_pixels_per_cycle, + .resync_fifo_dccg_dio = dcn314_resync_fifo_dccg_dio, .is_dp_dig_pixel_rate_div_policy = dcn32_is_dp_dig_pixel_rate_div_policy, .calculate_pix_rate_divider = dcn32_calculate_pix_rate_divider, .dsc_pg_control = dcn35_dsc_pg_control, |