From f73f6bd200c399d52d7147f66b956a01c93d7606 Mon Sep 17 00:00:00 2001 From: Mika Westerberg Date: Tue, 25 Oct 2022 09:46:20 +0300 Subject: spi: intel: Use ->replacement_op in intel_spi_hw_cycle() This way we do not need the SPI-NOR opcode -> Intel controller opcode mapping in the function anymore. Signed-off-by: Mika Westerberg Link: https://lore.kernel.org/r/20221025064623.22808-2-mika.westerberg@linux.intel.com Signed-off-by: Mark Brown --- drivers/spi/spi-intel.c | 52 ++++++++++++++++++++++--------------------------- 1 file changed, 23 insertions(+), 29 deletions(-) (limited to 'drivers/spi/spi-intel.c') diff --git a/drivers/spi/spi-intel.c b/drivers/spi/spi-intel.c index 605acb1bf4b0..2857d4086851 100644 --- a/drivers/spi/spi-intel.c +++ b/drivers/spi/spi-intel.c @@ -352,34 +352,25 @@ static int intel_spi_opcode_index(struct intel_spi *ispi, u8 opcode, int optype) return 0; } -static int intel_spi_hw_cycle(struct intel_spi *ispi, u8 opcode, size_t len) +static int intel_spi_hw_cycle(struct intel_spi *ispi, + const struct intel_spi_mem_op *iop, size_t len) { u32 val, status; int ret; + if (!iop->replacement_op) + return -EINVAL; + val = readl(ispi->base + HSFSTS_CTL); val &= ~(HSFSTS_CTL_FCYCLE_MASK | HSFSTS_CTL_FDBC_MASK); - switch (opcode) { - case SPINOR_OP_RDID: - val |= HSFSTS_CTL_FCYCLE_RDID; - break; - case SPINOR_OP_WRSR: - val |= HSFSTS_CTL_FCYCLE_WRSR; - break; - case SPINOR_OP_RDSR: - val |= HSFSTS_CTL_FCYCLE_RDSR; - break; - default: - return -EINVAL; - } - if (len > INTEL_SPI_FIFO_SZ) return -EINVAL; val |= (len - 1) << HSFSTS_CTL_FDBC_SHIFT; val |= HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE; val |= HSFSTS_CTL_FGO; + val |= iop->replacement_op; writel(val, ispi->base + HSFSTS_CTL); ret = intel_spi_wait_hw_busy(ispi); @@ -483,7 +474,7 @@ static int intel_spi_read_reg(struct intel_spi *ispi, const struct spi_mem *mem, ret = intel_spi_sw_cycle(ispi, opcode, nbytes, OPTYPE_READ_NO_ADDR); else - ret = intel_spi_hw_cycle(ispi, opcode, nbytes); + ret = intel_spi_hw_cycle(ispi, iop, nbytes); if (ret) return ret; @@ -548,7 +539,7 @@ static int intel_spi_write_reg(struct intel_spi *ispi, const struct spi_mem *mem if (ispi->swseq_reg) return intel_spi_sw_cycle(ispi, opcode, nbytes, OPTYPE_WRITE_NO_ADDR); - return intel_spi_hw_cycle(ispi, opcode, nbytes); + return intel_spi_hw_cycle(ispi, iop, nbytes); } static int intel_spi_read(struct intel_spi *ispi, const struct spi_mem *mem, @@ -912,18 +903,21 @@ static const struct spi_controller_mem_ops intel_spi_mem_ops = { */ #define INTEL_SPI_GENERIC_OPS \ /* Status register operations */ \ - INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 1), \ - SPI_MEM_OP_NO_ADDR, \ - INTEL_SPI_OP_DATA_IN(1), \ - intel_spi_read_reg), \ - INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR, 1), \ - SPI_MEM_OP_NO_ADDR, \ - INTEL_SPI_OP_DATA_IN(1), \ - intel_spi_read_reg), \ - INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRSR, 1), \ - SPI_MEM_OP_NO_ADDR, \ - INTEL_SPI_OP_DATA_OUT(1), \ - intel_spi_write_reg), \ + INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 1), \ + SPI_MEM_OP_NO_ADDR, \ + INTEL_SPI_OP_DATA_IN(1), \ + intel_spi_read_reg, \ + HSFSTS_CTL_FCYCLE_RDID), \ + INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_RDSR, 1), \ + SPI_MEM_OP_NO_ADDR, \ + INTEL_SPI_OP_DATA_IN(1), \ + intel_spi_read_reg, \ + HSFSTS_CTL_FCYCLE_RDSR), \ + INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_WRSR, 1), \ + SPI_MEM_OP_NO_ADDR, \ + INTEL_SPI_OP_DATA_OUT(1), \ + intel_spi_write_reg, \ + HSFSTS_CTL_FCYCLE_WRSR), \ /* Normal read */ \ INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ, 1), \ INTEL_SPI_OP_ADDR(3), \ -- cgit v1.2.3 From 8a9a784fb337cfd07f305faf5358335d4c12a788 Mon Sep 17 00:00:00 2001 From: Mika Westerberg Date: Tue, 25 Oct 2022 09:46:21 +0300 Subject: spi: intel: Implement adjust_op_size() This allows us to get rid of the checks in the intel_spi_[sh]w_cycle() and makes it possible for the SPI-NOR core to split the transaction into smaller chunks as needed. Signed-off-by: Mika Westerberg Link: https://lore.kernel.org/r/20221025064623.22808-3-mika.westerberg@linux.intel.com Signed-off-by: Mark Brown --- drivers/spi/spi-intel.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'drivers/spi/spi-intel.c') diff --git a/drivers/spi/spi-intel.c b/drivers/spi/spi-intel.c index 2857d4086851..431a6f97daf2 100644 --- a/drivers/spi/spi-intel.c +++ b/drivers/spi/spi-intel.c @@ -363,10 +363,6 @@ static int intel_spi_hw_cycle(struct intel_spi *ispi, val = readl(ispi->base + HSFSTS_CTL); val &= ~(HSFSTS_CTL_FCYCLE_MASK | HSFSTS_CTL_FDBC_MASK); - - if (len > INTEL_SPI_FIFO_SZ) - return -EINVAL; - val |= (len - 1) << HSFSTS_CTL_FDBC_SHIFT; val |= HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE; val |= HSFSTS_CTL_FGO; @@ -397,9 +393,6 @@ static int intel_spi_sw_cycle(struct intel_spi *ispi, u8 opcode, size_t len, if (ret < 0) return ret; - if (len > INTEL_SPI_FIFO_SZ) - return -EINVAL; - /* * Always clear it after each SW sequencer operation regardless * of whether it is successful or not. @@ -704,6 +697,12 @@ static int intel_spi_erase(struct intel_spi *ispi, const struct spi_mem *mem, return 0; } +static int intel_spi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) +{ + op->data.nbytes = clamp_val(op->data.nbytes, 0, INTEL_SPI_FIFO_SZ); + return 0; +} + static bool intel_spi_cmp_mem_op(const struct intel_spi_mem_op *iop, const struct spi_mem_op *op) { @@ -844,6 +843,7 @@ static ssize_t intel_spi_dirmap_write(struct spi_mem_dirmap_desc *desc, u64 offs } static const struct spi_controller_mem_ops intel_spi_mem_ops = { + .adjust_op_size = intel_spi_adjust_op_size, .supports_op = intel_spi_supports_mem_op, .exec_op = intel_spi_exec_mem_op, .get_name = intel_spi_get_name, -- cgit v1.2.3 From 43f173e7e508ede3d6f5411b9ffbb33d6d284211 Mon Sep 17 00:00:00 2001 From: Mika Westerberg Date: Tue, 25 Oct 2022 09:46:22 +0300 Subject: spi: intel: Take possible chip address into account in intel_spi_read/write_reg() The SPI-NOR operation can have non-zero chip address as well so take this into account in intel_spi_read/write_reg(). Signed-off-by: Mika Westerberg Link: https://lore.kernel.org/r/20221025064623.22808-4-mika.westerberg@linux.intel.com Signed-off-by: Mark Brown --- drivers/spi/spi-intel.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'drivers/spi/spi-intel.c') diff --git a/drivers/spi/spi-intel.c b/drivers/spi/spi-intel.c index 431a6f97daf2..4d8fda991e7b 100644 --- a/drivers/spi/spi-intel.c +++ b/drivers/spi/spi-intel.c @@ -457,11 +457,12 @@ static int intel_spi_read_reg(struct intel_spi *ispi, const struct spi_mem *mem, const struct intel_spi_mem_op *iop, const struct spi_mem_op *op) { + u32 addr = intel_spi_chip_addr(ispi, mem) + op->addr.val; size_t nbytes = op->data.nbytes; u8 opcode = op->cmd.opcode; int ret; - writel(intel_spi_chip_addr(ispi, mem), ispi->base + FADDR); + writel(addr, ispi->base + FADDR); if (ispi->swseq_reg) ret = intel_spi_sw_cycle(ispi, opcode, nbytes, @@ -479,6 +480,7 @@ static int intel_spi_write_reg(struct intel_spi *ispi, const struct spi_mem *mem const struct intel_spi_mem_op *iop, const struct spi_mem_op *op) { + u32 addr = intel_spi_chip_addr(ispi, mem) + op->addr.val; size_t nbytes = op->data.nbytes; u8 opcode = op->cmd.opcode; int ret; @@ -522,7 +524,7 @@ static int intel_spi_write_reg(struct intel_spi *ispi, const struct spi_mem *mem if (opcode == SPINOR_OP_WRDI) return 0; - writel(intel_spi_chip_addr(ispi, mem), ispi->base + FADDR); + writel(addr, ispi->base + FADDR); /* Write the value beforehand */ ret = intel_spi_write_block(ispi, op->data.buf.out, nbytes); -- cgit v1.2.3 From ec4a04aa6962fff3cfa63d70536537844f7446d2 Mon Sep 17 00:00:00 2001 From: Mika Westerberg Date: Tue, 25 Oct 2022 09:46:23 +0300 Subject: spi: intel: Add support for SFDP opcode The Intel SPI-NOR controller supports SFDP (Serial Flash Discoverable Parameter) opcode so add it to the list of supported opcodes. Signed-off-by: Mika Westerberg Link: https://lore.kernel.org/r/20221025064623.22808-5-mika.westerberg@linux.intel.com Signed-off-by: Mark Brown --- drivers/spi/spi-intel.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers/spi/spi-intel.c') diff --git a/drivers/spi/spi-intel.c b/drivers/spi/spi-intel.c index 4d8fda991e7b..71c36ad778fc 100644 --- a/drivers/spi/spi-intel.c +++ b/drivers/spi/spi-intel.c @@ -33,6 +33,7 @@ #define HSFSTS_CTL_FCYCLE_WRITE (0x02 << HSFSTS_CTL_FCYCLE_SHIFT) #define HSFSTS_CTL_FCYCLE_ERASE (0x03 << HSFSTS_CTL_FCYCLE_SHIFT) #define HSFSTS_CTL_FCYCLE_ERASE_64K (0x04 << HSFSTS_CTL_FCYCLE_SHIFT) +#define HSFSTS_CTL_FCYCLE_RDSFDP (0x05 << HSFSTS_CTL_FCYCLE_SHIFT) #define HSFSTS_CTL_FCYCLE_RDID (0x06 << HSFSTS_CTL_FCYCLE_SHIFT) #define HSFSTS_CTL_FCYCLE_WRSR (0x07 << HSFSTS_CTL_FCYCLE_SHIFT) #define HSFSTS_CTL_FCYCLE_RDSR (0x08 << HSFSTS_CTL_FCYCLE_SHIFT) @@ -920,6 +921,11 @@ static const struct spi_controller_mem_ops intel_spi_mem_ops = { INTEL_SPI_OP_DATA_OUT(1), \ intel_spi_write_reg, \ HSFSTS_CTL_FCYCLE_WRSR), \ + INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_RDSFDP, 1), \ + INTEL_SPI_OP_ADDR(3), \ + INTEL_SPI_OP_DATA_IN(1), \ + intel_spi_read_reg, \ + HSFSTS_CTL_FCYCLE_RDSFDP), \ /* Normal read */ \ INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ, 1), \ INTEL_SPI_OP_ADDR(3), \ -- cgit v1.2.3