From 16292bed9c56a20715d942fd5d9e025f01fa65fe Mon Sep 17 00:00:00 2001 From: Gayatri Kammela Date: Fri, 24 Jan 2020 10:59:28 -0800 Subject: platform/x86: intel_pmc_core: Add Atom based Jasper Lake (JSL) platform support Add Jasper Lake to the list of the platforms that intel_pmc_core driver supports for pmc_core device. Just like Ice Lake, Tiger Lake and Elkhart Lake, Jasper Lake can also reuse all the Cannon Lake PCH IPs. Also, it uses the same PCH IPs of Tiger Lake, no additional effort is needed to enable but to simply reuse them. Cc: Srinivas Pandruvada Cc: Andy Shevchenko Cc: David Box Signed-off-by: Gayatri Kammela Signed-off-by: Andy Shevchenko --- drivers/platform/x86/intel_pmc_core.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'drivers/platform/x86/intel_pmc_core.c') diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c index 144faa8bad3d..f85c112f8c2c 100644 --- a/drivers/platform/x86/intel_pmc_core.c +++ b/drivers/platform/x86/intel_pmc_core.c @@ -193,7 +193,7 @@ static const struct pmc_bit_map cnp_pfear_map[] = { {"Fuse", BIT(6)}, /* * Reserved for Cannon Lake but valid for Ice Lake, Comet Lake, - * Tiger Lake and Elkhart Lake. + * Tiger Lake, Elkhart Lake and Jasper Lake. */ {"SBR8", BIT(7)}, @@ -240,7 +240,7 @@ static const struct pmc_bit_map cnp_pfear_map[] = { {"HDA_PGD6", BIT(4)}, /* * Reserved for Cannon Lake but valid for Ice Lake, Comet Lake, - * Tiger Lake and ELkhart Lake. + * Tiger Lake, ELkhart Lake and Jasper Lake. */ {"PSF6", BIT(5)}, {"PSF7", BIT(6)}, @@ -273,7 +273,7 @@ static const struct pmc_bit_map *ext_icl_pfear_map[] = { }; static const struct pmc_bit_map tgl_pfear_map[] = { - /* Tiger Lake and Elkhart Lake generation onwards only */ + /* Tiger Lake, Elkhart Lake and Jasper Lake generation onwards only */ {"PSF9", BIT(0)}, {"RES_66", BIT(1)}, {"RES_67", BIT(2)}, @@ -883,6 +883,7 @@ static const struct x86_cpu_id intel_pmc_core_ids[] = { INTEL_CPU_FAM6(TIGERLAKE_L, tgl_reg_map), INTEL_CPU_FAM6(TIGERLAKE, tgl_reg_map), INTEL_CPU_FAM6(ATOM_TREMONT, tgl_reg_map), + INTEL_CPU_FAM6(ATOM_TREMONT_L, tgl_reg_map), {} }; -- cgit v1.2.3 From a45096ac70e59498ef3d1fe67ab6a10dbccf59ef Mon Sep 17 00:00:00 2001 From: Gayatri Kammela Date: Tue, 4 Feb 2020 15:01:54 -0800 Subject: platform/x86: intel_pmc_core: Add debugfs entry to access sub-state residencies Prior to Tiger Lake, the platforms that support pmc_core have no sub-states of S0ix. Tiger Lake has 8 sub-states/low power modes of S0ix ranging from S0i2.0-S0i2.2 and S0i3.0-S0i3.4, simply represented as S0ix.y. Create a debugfs entry to access residency of each sub-state. Cc: Srinivas Pandruvada Cc: Andy Shevchenko Cc: David Box Signed-off-by: David Box Signed-off-by: Gayatri Kammela Signed-off-by: Andy Shevchenko --- drivers/platform/x86/intel_pmc_core.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'drivers/platform/x86/intel_pmc_core.c') diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c index f85c112f8c2c..08aac03010c9 100644 --- a/drivers/platform/x86/intel_pmc_core.c +++ b/drivers/platform/x86/intel_pmc_core.c @@ -422,6 +422,8 @@ static const struct pmc_reg_map tgl_reg_map = { .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET, .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT, .ltr_ignore_max = TGL_NUM_IP_IGN_ALLOWED, + .lpm_en_offset = TGL_LPM_EN_OFFSET, + .lpm_residency_offset = TGL_LPM_RESIDENCY_OFFSET, }; static inline u32 pmc_core_reg_read(struct pmc_dev *pmcdev, int reg_offset) @@ -794,6 +796,26 @@ static int pmc_core_ltr_show(struct seq_file *s, void *unused) } DEFINE_SHOW_ATTRIBUTE(pmc_core_ltr); +static int pmc_core_substate_res_show(struct seq_file *s, void *unused) +{ + struct pmc_dev *pmcdev = s->private; + u32 offset = pmcdev->map->lpm_residency_offset; + u32 lpm_en; + int index; + + lpm_en = pmc_core_reg_read(pmcdev, pmcdev->map->lpm_en_offset); + seq_printf(s, "status substate residency\n"); + for (index = 0; lpm_modes[index]; index++) { + seq_printf(s, "%7s %7s %-15u\n", + BIT(index) & lpm_en ? "Enabled" : " ", + lpm_modes[index], pmc_core_reg_read(pmcdev, offset)); + offset += 4; + } + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(pmc_core_substate_res); + static int pmc_core_pkgc_show(struct seq_file *s, void *unused) { struct pmc_dev *pmcdev = s->private; @@ -859,6 +881,12 @@ static void pmc_core_dbgfs_register(struct pmc_dev *pmcdev) debugfs_create_bool("slp_s0_dbg_latch", 0644, dir, &slps0_dbg_latch); } + + if (pmcdev->map->lpm_en_offset) { + debugfs_create_file("substate_residencies", 0444, + pmcdev->dbgfs_dir, pmcdev, + &pmc_core_substate_res_fops); + } } #else static inline void pmc_core_dbgfs_register(struct pmc_dev *pmcdev) -- cgit v1.2.3 From f632817d5ef369a6f433449a1b8fa26627fc40e0 Mon Sep 17 00:00:00 2001 From: Gayatri Kammela Date: Tue, 4 Feb 2020 15:01:55 -0800 Subject: platform/x86: intel_pmc_core: Add debugfs entry for low power mode status registers Tiger Lake has 6 status registers that are memory mapped. These registers show the status of the low power mode requirements. The registers are latched on every C10 entry or exit and on every s0ix.y entry/exit. Accessing these registers is useful for debugging any low power related activities. Thus, add debugfs entry to access low power mode status registers. Cc: Srinivas Pandruvada Cc: Andy Shevchenko Cc: David Box Signed-off-by: David Box Signed-off-by: Gayatri Kammela Signed-off-by: Andy Shevchenko --- drivers/platform/x86/intel_pmc_core.c | 188 ++++++++++++++++++++++++++++++++++ 1 file changed, 188 insertions(+) (limited to 'drivers/platform/x86/intel_pmc_core.c') diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c index 08aac03010c9..43f37001a4ee 100644 --- a/drivers/platform/x86/intel_pmc_core.c +++ b/drivers/platform/x86/intel_pmc_core.c @@ -408,6 +408,152 @@ static const struct pmc_reg_map icl_reg_map = { .ltr_ignore_max = ICL_NUM_IP_IGN_ALLOWED, }; +static const struct pmc_bit_map tgl_lpm0_map[] = { + {"USB2PLL_OFF_STS", BIT(18)}, + {"PCIe/USB3.1_Gen2PLL_OFF_STS", BIT(19)}, + {"PCIe_Gen3PLL_OFF_STS", BIT(20)}, + {"OPIOPLL_OFF_STS", BIT(21)}, + {"OCPLL_OFF_STS", BIT(22)}, + {"AudioPLL_OFF_STS", BIT(23)}, + {"MIPIPLL_OFF_STS", BIT(24)}, + {"Fast_XTAL_Osc_OFF_STS", BIT(25)}, + {"AC_Ring_Osc_OFF_STS", BIT(26)}, + {"MC_Ring_Osc_OFF_STS", BIT(27)}, + {"SATAPLL_OFF_STS", BIT(29)}, + {"XTAL_USB2PLL_OFF_STS", BIT(31)}, + {} +}; + +static const struct pmc_bit_map tgl_lpm1_map[] = { + {"SPI_PG_STS", BIT(2)}, + {"xHCI_PG_STS", BIT(3)}, + {"PCIe_Ctrller_A_PG_STS", BIT(4)}, + {"PCIe_Ctrller_B_PG_STS", BIT(5)}, + {"PCIe_Ctrller_C_PG_STS", BIT(6)}, + {"GBE_PG_STS", BIT(7)}, + {"SATA_PG_STS", BIT(8)}, + {"HDA0_PG_STS", BIT(9)}, + {"HDA1_PG_STS", BIT(10)}, + {"HDA2_PG_STS", BIT(11)}, + {"HDA3_PG_STS", BIT(12)}, + {"PCIe_Ctrller_D_PG_STS", BIT(13)}, + {"ISIO_PG_STS", BIT(14)}, + {"SMB_PG_STS", BIT(16)}, + {"ISH_PG_STS", BIT(17)}, + {"ITH_PG_STS", BIT(19)}, + {"SDX_PG_STS", BIT(20)}, + {"xDCI_PG_STS", BIT(25)}, + {"DCI_PG_STS", BIT(26)}, + {"CSME0_PG_STS", BIT(27)}, + {"CSME_KVM_PG_STS", BIT(28)}, + {"CSME1_PG_STS", BIT(29)}, + {"CSME_CLINK_PG_STS", BIT(30)}, + {"CSME2_PG_STS", BIT(31)}, + {} +}; + +static const struct pmc_bit_map tgl_lpm2_map[] = { + {"ADSP_D3_STS", BIT(0)}, + {"SATA_D3_STS", BIT(1)}, + {"xHCI0_D3_STS", BIT(2)}, + {"xDCI1_D3_STS", BIT(5)}, + {"SDX_D3_STS", BIT(6)}, + {"EMMC_D3_STS", BIT(7)}, + {"IS_D3_STS", BIT(8)}, + {"THC0_D3_STS", BIT(9)}, + {"THC1_D3_STS", BIT(10)}, + {"GBE_D3_STS", BIT(11)}, + {"GBE_TSN_D3_STS", BIT(12)}, + {} +}; + +static const struct pmc_bit_map tgl_lpm3_map[] = { + {"GPIO_COM0_VNN_REQ_STS", BIT(1)}, + {"GPIO_COM1_VNN_REQ_STS", BIT(2)}, + {"GPIO_COM2_VNN_REQ_STS", BIT(3)}, + {"GPIO_COM3_VNN_REQ_STS", BIT(4)}, + {"GPIO_COM4_VNN_REQ_STS", BIT(5)}, + {"GPIO_COM5_VNN_REQ_STS", BIT(6)}, + {"Audio_VNN_REQ_STS", BIT(7)}, + {"ISH_VNN_REQ_STS", BIT(8)}, + {"CNVI_VNN_REQ_STS", BIT(9)}, + {"eSPI_VNN_REQ_STS", BIT(10)}, + {"Display_VNN_REQ_STS", BIT(11)}, + {"DTS_VNN_REQ_STS", BIT(12)}, + {"SMBUS_VNN_REQ_STS", BIT(14)}, + {"CSME_VNN_REQ_STS", BIT(15)}, + {"SMLINK0_VNN_REQ_STS", BIT(16)}, + {"SMLINK1_VNN_REQ_STS", BIT(17)}, + {"CLINK_VNN_REQ_STS", BIT(20)}, + {"DCI_VNN_REQ_STS", BIT(21)}, + {"ITH_VNN_REQ_STS", BIT(22)}, + {"CSME_VNN_REQ_STS", BIT(24)}, + {"GBE_VNN_REQ_STS", BIT(25)}, + {} +}; + +static const struct pmc_bit_map tgl_lpm4_map[] = { + {"CPU_C10_REQ_STS_0", BIT(0)}, + {"PCIe_LPM_En_REQ_STS_3", BIT(3)}, + {"ITH_REQ_STS_5", BIT(5)}, + {"CNVI_REQ_STS_6", BIT(6)}, + {"ISH_REQ_STS_7", BIT(7)}, + {"USB2_SUS_PG_Sys_REQ_STS_10", BIT(10)}, + {"PCIe_Clk_REQ_STS_12", BIT(12)}, + {"MPHY_Core_DL_REQ_STS_16", BIT(16)}, + {"Break-even_En_REQ_STS_17", BIT(17)}, + {"Auto-demo_En_REQ_STS_18", BIT(18)}, + {"MPHY_SUS_REQ_STS_22", BIT(22)}, + {"xDCI_attached_REQ_STS_24", BIT(24)}, + {} +}; + +static const struct pmc_bit_map tgl_lpm5_map[] = { + {"LSX_Wake0_En_STS", BIT(0)}, + {"LSX_Wake0_Pol_STS", BIT(1)}, + {"LSX_Wake1_En_STS", BIT(2)}, + {"LSX_Wake1_Pol_STS", BIT(3)}, + {"LSX_Wake2_En_STS", BIT(4)}, + {"LSX_Wake2_Pol_STS", BIT(5)}, + {"LSX_Wake3_En_STS", BIT(6)}, + {"LSX_Wake3_Pol_STS", BIT(7)}, + {"LSX_Wake4_En_STS", BIT(8)}, + {"LSX_Wake4_Pol_STS", BIT(9)}, + {"LSX_Wake5_En_STS", BIT(10)}, + {"LSX_Wake5_Pol_STS", BIT(11)}, + {"LSX_Wake6_En_STS", BIT(12)}, + {"LSX_Wake6_Pol_STS", BIT(13)}, + {"LSX_Wake7_En_STS", BIT(14)}, + {"LSX_Wake7_Pol_STS", BIT(15)}, + {"Intel_Se_IO_Wake0_En_STS", BIT(16)}, + {"Intel_Se_IO_Wake0_Pol_STS", BIT(17)}, + {"Intel_Se_IO_Wake1_En_STS", BIT(18)}, + {"Intel_Se_IO_Wake1_Pol_STS", BIT(19)}, + {"Int_Timer_SS_Wake0_En_STS", BIT(20)}, + {"Int_Timer_SS_Wake0_Pol_STS", BIT(21)}, + {"Int_Timer_SS_Wake1_En_STS", BIT(22)}, + {"Int_Timer_SS_Wake1_Pol_STS", BIT(23)}, + {"Int_Timer_SS_Wake2_En_STS", BIT(24)}, + {"Int_Timer_SS_Wake2_Pol_STS", BIT(25)}, + {"Int_Timer_SS_Wake3_En_STS", BIT(26)}, + {"Int_Timer_SS_Wake3_Pol_STS", BIT(27)}, + {"Int_Timer_SS_Wake4_En_STS", BIT(28)}, + {"Int_Timer_SS_Wake4_Pol_STS", BIT(29)}, + {"Int_Timer_SS_Wake5_En_STS", BIT(30)}, + {"Int_Timer_SS_Wake5_Pol_STS", BIT(31)}, + {} +}; + +static const struct pmc_bit_map *tgl_lpm_maps[] = { + tgl_lpm0_map, + tgl_lpm1_map, + tgl_lpm2_map, + tgl_lpm3_map, + tgl_lpm4_map, + tgl_lpm5_map, + NULL +}; + static const struct pmc_reg_map tgl_reg_map = { .pfear_sts = ext_tgl_pfear_map, .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET, @@ -424,6 +570,8 @@ static const struct pmc_reg_map tgl_reg_map = { .ltr_ignore_max = TGL_NUM_IP_IGN_ALLOWED, .lpm_en_offset = TGL_LPM_EN_OFFSET, .lpm_residency_offset = TGL_LPM_RESIDENCY_OFFSET, + .lpm_sts = tgl_lpm_maps, + .lpm_status_offset = TGL_LPM_STATUS_OFFSET, }; static inline u32 pmc_core_reg_read(struct pmc_dev *pmcdev, int reg_offset) @@ -816,6 +964,40 @@ static int pmc_core_substate_res_show(struct seq_file *s, void *unused) } DEFINE_SHOW_ATTRIBUTE(pmc_core_substate_res); +static void pmc_core_lpm_display(struct pmc_dev *pmcdev, struct seq_file *s, + u32 offset, const char *str, + const struct pmc_bit_map **maps) +{ + u32 lpm_regs[ARRAY_SIZE(tgl_lpm_maps)-1]; + int index, idx, len = 32, bit_mask; + + for (index = 0; tgl_lpm_maps[index]; index++) { + lpm_regs[index] = pmc_core_reg_read(pmcdev, offset); + offset += 4; + } + + for (idx = 0; maps[idx]; idx++) { + seq_printf(s, "\nLPM_%s_%d:\t0x%x\n", str, idx, lpm_regs[idx]); + for (index = 0; maps[idx][index].name && index < len; index++) { + bit_mask = maps[idx][index].bit_mask; + seq_printf(s, "%-30s %-30d\n", maps[idx][index].name, + lpm_regs[idx] & bit_mask ? 1 : 0); + } + } +} + +static int pmc_core_substate_sts_regs_show(struct seq_file *s, void *unused) +{ + struct pmc_dev *pmcdev = s->private; + const struct pmc_bit_map **maps = pmcdev->map->lpm_sts; + u32 offset = pmcdev->map->lpm_status_offset; + + pmc_core_lpm_display(pmcdev, s, offset, "STATUS", maps); + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(pmc_core_substate_sts_regs); + static int pmc_core_pkgc_show(struct seq_file *s, void *unused) { struct pmc_dev *pmcdev = s->private; @@ -887,6 +1069,12 @@ static void pmc_core_dbgfs_register(struct pmc_dev *pmcdev) pmcdev->dbgfs_dir, pmcdev, &pmc_core_substate_res_fops); } + + if (pmcdev->map->lpm_status_offset) { + debugfs_create_file("substate_status_registers", 0444, + pmcdev->dbgfs_dir, pmcdev, + &pmc_core_substate_sts_regs_fops); + } } #else static inline void pmc_core_dbgfs_register(struct pmc_dev *pmcdev) -- cgit v1.2.3 From 4d6a63e0b99ea4ba7f718ab084ebf566b7d1585f Mon Sep 17 00:00:00 2001 From: Gayatri Kammela Date: Tue, 4 Feb 2020 15:01:56 -0800 Subject: platform/x86: intel_pmc_core: Refactor the driver by removing redundant code pmc_core_slps0_dbg_show() is responsible for displaying debug registers through slp_s0_debug_status entry. The driver uses the same but redundant code to dump these debug registers for an S0ix failure. Hence, refactor the driver by removing redundant code and reuse the same function that both dumps registers through slp_s0_debug_status entry and in resume for an S0ix failure. The changes in this patch are preparatory, so platforms that support low power sub-states can dump the debug registers when the attempt to enter low power states are unsuccessful. Cc: Srinivas Pandruvada Cc: Andy Shevchenko Cc: David Box Suggested-by: Andy Shevchenko Signed-off-by: Gayatri Kammela Signed-off-by: Andy Shevchenko --- drivers/platform/x86/intel_pmc_core.c | 48 +++++++++++++++++------------------ 1 file changed, 23 insertions(+), 25 deletions(-) (limited to 'drivers/platform/x86/intel_pmc_core.c') diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c index 43f37001a4ee..8792b4658672 100644 --- a/drivers/platform/x86/intel_pmc_core.c +++ b/drivers/platform/x86/intel_pmc_core.c @@ -845,30 +845,41 @@ out_unlock: mutex_unlock(&pmcdev->lock); } -static int pmc_core_slps0_dbg_show(struct seq_file *s, void *unused) +static void pmc_core_slps0_display(struct pmc_dev *pmcdev, struct device *dev, + struct seq_file *s) { - struct pmc_dev *pmcdev = s->private; const struct pmc_bit_map **maps = pmcdev->map->slps0_dbg_maps; const struct pmc_bit_map *map; - int offset; + int offset = pmcdev->map->slps0_dbg_offset; u32 data; - pmc_core_slps0_dbg_latch(pmcdev, false); - offset = pmcdev->map->slps0_dbg_offset; while (*maps) { map = *maps; data = pmc_core_reg_read(pmcdev, offset); offset += 4; while (map->name) { - seq_printf(s, "SLP_S0_DBG: %-32s\tState: %s\n", - map->name, - data & map->bit_mask ? - "Yes" : "No"); + if (dev) + dev_dbg(dev, "SLP_S0_DBG: %-32s\tState: %s\n", + map->name, + data & map->bit_mask ? "Yes" : "No"); + if (s) + seq_printf(s, "SLP_S0_DBG: %-32s\tState: %s\n", + map->name, + data & map->bit_mask ? "Yes" : "No"); ++map; } ++maps; } +} + +static int pmc_core_slps0_dbg_show(struct seq_file *s, void *unused) +{ + struct pmc_dev *pmcdev = s->private; + + pmc_core_slps0_dbg_latch(pmcdev, false); + pmc_core_slps0_display(pmcdev, NULL, s); pmc_core_slps0_dbg_latch(pmcdev, true); + return 0; } DEFINE_SHOW_ATTRIBUTE(pmc_core_slps0_dbg); @@ -1264,10 +1275,6 @@ static inline bool pmc_core_is_s0ix_failed(struct pmc_dev *pmcdev) static int pmc_core_resume(struct device *dev) { struct pmc_dev *pmcdev = dev_get_drvdata(dev); - const struct pmc_bit_map **maps = pmcdev->map->slps0_dbg_maps; - int offset = pmcdev->map->slps0_dbg_offset; - const struct pmc_bit_map *map; - u32 data; if (!pmcdev->check_counters) return 0; @@ -1285,18 +1292,9 @@ static int pmc_core_resume(struct device *dev) /* The real interesting case - S0ix failed - lets ask PMC why. */ dev_warn(dev, "CPU did not enter SLP_S0!!! (S0ix cnt=%llu)\n", pmcdev->s0ix_counter); - while (*maps) { - map = *maps; - data = pmc_core_reg_read(pmcdev, offset); - offset += 4; - while (map->name) { - dev_dbg(dev, "SLP_S0_DBG: %-32s\tState: %s\n", - map->name, - data & map->bit_mask ? "Yes" : "No"); - map++; - } - maps++; - } + if (pmcdev->map->slps0_dbg_maps) + pmc_core_slps0_display(pmcdev, dev, NULL); + return 0; } -- cgit v1.2.3 From a018e28f0880c1eaa72b09d2ec64831024d149a6 Mon Sep 17 00:00:00 2001 From: Gayatri Kammela Date: Tue, 4 Feb 2020 15:01:57 -0800 Subject: platform/x86: intel_pmc_core: Remove slp_s0 attributes from tgl_reg_map If platforms such as Tiger Lake has sub-states of S0ix, then both slp_s0_debug_status and slp_s0_dbg_latch entries become invalid. Thus, remove slp_s0_offset and slp_s0_dbg_maps attributes from tgl_reg_map, so that both the entries are not created. Cc: Srinivas Pandruvada Cc: Andy Shevchenko Cc: David Box Suggested-by: David Box Signed-off-by: Gayatri Kammela Signed-off-by: Andy Shevchenko --- drivers/platform/x86/intel_pmc_core.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'drivers/platform/x86/intel_pmc_core.c') diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c index 8792b4658672..97511a700d45 100644 --- a/drivers/platform/x86/intel_pmc_core.c +++ b/drivers/platform/x86/intel_pmc_core.c @@ -556,8 +556,6 @@ static const struct pmc_bit_map *tgl_lpm_maps[] = { static const struct pmc_reg_map tgl_reg_map = { .pfear_sts = ext_tgl_pfear_map, - .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET, - .slps0_dbg_maps = cnp_slps0_dbg_maps, .ltr_show_sts = cnp_ltr_show_map, .msr_sts = msr_map, .slps0_dbg_offset = CNP_PMC_SLPS0_DBG_OFFSET, -- cgit v1.2.3 From 913f984a8347ea967ee9693dfa1e15da78e64661 Mon Sep 17 00:00:00 2001 From: Gayatri Kammela Date: Tue, 4 Feb 2020 15:01:58 -0800 Subject: platform/x86: intel_pmc_core: Add an additional parameter to pmc_core_lpm_display() Add a device pointer of type struct device as an additional parameter to pmc_core_lpm_display(), so that the driver can re-use it to dump the debug registers in resume for an S0ix failure. Cc: Srinivas Pandruvada Cc: Andy Shevchenko Cc: David Box Signed-off-by: Gayatri Kammela Signed-off-by: Andy Shevchenko --- drivers/platform/x86/intel_pmc_core.c | 24 ++++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) (limited to 'drivers/platform/x86/intel_pmc_core.c') diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c index 97511a700d45..bddde30fd5f3 100644 --- a/drivers/platform/x86/intel_pmc_core.c +++ b/drivers/platform/x86/intel_pmc_core.c @@ -973,8 +973,9 @@ static int pmc_core_substate_res_show(struct seq_file *s, void *unused) } DEFINE_SHOW_ATTRIBUTE(pmc_core_substate_res); -static void pmc_core_lpm_display(struct pmc_dev *pmcdev, struct seq_file *s, - u32 offset, const char *str, +static void pmc_core_lpm_display(struct pmc_dev *pmcdev, struct device *dev, + struct seq_file *s, u32 offset, + const char *str, const struct pmc_bit_map **maps) { u32 lpm_regs[ARRAY_SIZE(tgl_lpm_maps)-1]; @@ -986,11 +987,22 @@ static void pmc_core_lpm_display(struct pmc_dev *pmcdev, struct seq_file *s, } for (idx = 0; maps[idx]; idx++) { - seq_printf(s, "\nLPM_%s_%d:\t0x%x\n", str, idx, lpm_regs[idx]); + if (dev) + dev_dbg(dev, "\nLPM_%s_%d:\t0x%x\n", str, idx, + lpm_regs[idx]); + if (s) + seq_printf(s, "\nLPM_%s_%d:\t0x%x\n", str, idx, + lpm_regs[idx]); for (index = 0; maps[idx][index].name && index < len; index++) { bit_mask = maps[idx][index].bit_mask; - seq_printf(s, "%-30s %-30d\n", maps[idx][index].name, - lpm_regs[idx] & bit_mask ? 1 : 0); + if (dev) + dev_dbg(dev, "%-30s %-30d\n", + maps[idx][index].name, + lpm_regs[idx] & bit_mask ? 1 : 0); + if (s) + seq_printf(s, "%-30s %-30d\n", + maps[idx][index].name, + lpm_regs[idx] & bit_mask ? 1 : 0); } } } @@ -1001,7 +1013,7 @@ static int pmc_core_substate_sts_regs_show(struct seq_file *s, void *unused) const struct pmc_bit_map **maps = pmcdev->map->lpm_sts; u32 offset = pmcdev->map->lpm_status_offset; - pmc_core_lpm_display(pmcdev, s, offset, "STATUS", maps); + pmc_core_lpm_display(pmcdev, NULL, s, offset, "STATUS", maps); return 0; } -- cgit v1.2.3 From 2e36ac08a98829b132a9d0bf1ca281af1a931747 Mon Sep 17 00:00:00 2001 From: Gayatri Kammela Date: Tue, 4 Feb 2020 15:01:59 -0800 Subject: platform/x86: intel_pmc_core: Dump low power status registers on an S0ix.y failure Platforms prior to Tiger Lake has no sub-states of S0ix and accessing device PM states that are latched whenever there is a PC10 entry is possible with the help of slp_s0_debug_status and slp_s0_dbg_latch debugfs entries. If a platform has sub-states of S0ix, no such entries are created. Hence, dump low power status registers on resume When any attempt to enter any low power state was unsuccessful. Cc: Srinivas Pandruvada Cc: Andy Shevchenko Cc: David Box Suggested-by: David Box Signed-off-by: Gayatri Kammela Signed-off-by: Andy Shevchenko --- drivers/platform/x86/intel_pmc_core.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/platform/x86/intel_pmc_core.c') diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c index bddde30fd5f3..fe5fddc808c4 100644 --- a/drivers/platform/x86/intel_pmc_core.c +++ b/drivers/platform/x86/intel_pmc_core.c @@ -1285,6 +1285,8 @@ static inline bool pmc_core_is_s0ix_failed(struct pmc_dev *pmcdev) static int pmc_core_resume(struct device *dev) { struct pmc_dev *pmcdev = dev_get_drvdata(dev); + const struct pmc_bit_map **maps = pmcdev->map->lpm_sts; + int offset = pmcdev->map->lpm_status_offset; if (!pmcdev->check_counters) return 0; @@ -1304,6 +1306,8 @@ static int pmc_core_resume(struct device *dev) pmcdev->s0ix_counter); if (pmcdev->map->slps0_dbg_maps) pmc_core_slps0_display(pmcdev, dev, NULL); + if (pmcdev->map->lpm_sts) + pmc_core_lpm_display(pmcdev, dev, NULL, offset, "STATUS", maps); return 0; } -- cgit v1.2.3 From 7adb1e8aeeb5d4d88012568b2049599c1a247cf2 Mon Sep 17 00:00:00 2001 From: Gayatri Kammela Date: Tue, 4 Feb 2020 15:02:00 -0800 Subject: platform/x86: intel_pmc_core: Add debugfs support to access live status registers Just like status registers, Tiger Lake has another set of 6 registers that help with status of the low power mode requirements. They are latched on every PC10 entry/exit and S0ix.y entry/exit as well. Though status and live status registers show the status of same list of requirements, live status registers show the status of the low power mode requirements at the time of reading. Cc: Srinivas Pandruvada Cc: Andy Shevchenko Cc: David E. Box Signed-off-by: Gayatri Kammela Signed-off-by: Andy Shevchenko --- drivers/platform/x86/intel_pmc_core.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'drivers/platform/x86/intel_pmc_core.c') diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c index fe5fddc808c4..f4a36fbabf4c 100644 --- a/drivers/platform/x86/intel_pmc_core.c +++ b/drivers/platform/x86/intel_pmc_core.c @@ -570,6 +570,7 @@ static const struct pmc_reg_map tgl_reg_map = { .lpm_residency_offset = TGL_LPM_RESIDENCY_OFFSET, .lpm_sts = tgl_lpm_maps, .lpm_status_offset = TGL_LPM_STATUS_OFFSET, + .lpm_live_status_offset = TGL_LPM_LIVE_STATUS_OFFSET, }; static inline u32 pmc_core_reg_read(struct pmc_dev *pmcdev, int reg_offset) @@ -1019,6 +1020,18 @@ static int pmc_core_substate_sts_regs_show(struct seq_file *s, void *unused) } DEFINE_SHOW_ATTRIBUTE(pmc_core_substate_sts_regs); +static int pmc_core_substate_l_sts_regs_show(struct seq_file *s, void *unused) +{ + struct pmc_dev *pmcdev = s->private; + const struct pmc_bit_map **maps = pmcdev->map->lpm_sts; + u32 offset = pmcdev->map->lpm_live_status_offset; + + pmc_core_lpm_display(pmcdev, NULL, s, offset, "LIVE_STATUS", maps); + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(pmc_core_substate_l_sts_regs); + static int pmc_core_pkgc_show(struct seq_file *s, void *unused) { struct pmc_dev *pmcdev = s->private; @@ -1096,6 +1109,12 @@ static void pmc_core_dbgfs_register(struct pmc_dev *pmcdev) pmcdev->dbgfs_dir, pmcdev, &pmc_core_substate_sts_regs_fops); } + + if (pmcdev->map->lpm_status_offset) { + debugfs_create_file("substate_live_status_registers", 0444, + pmcdev->dbgfs_dir, pmcdev, + &pmc_core_substate_l_sts_regs_fops); + } } #else static inline void pmc_core_dbgfs_register(struct pmc_dev *pmcdev) -- cgit v1.2.3 From aae43c2bcdc1939c4c6a51b3e28460ada68f8c0c Mon Sep 17 00:00:00 2001 From: Gayatri Kammela Date: Thu, 27 Feb 2020 15:29:13 -0800 Subject: platform/x86: intel_pmc_core: Relocate pmc_core_*_display() to outside of CONFIG_DEBUG_FS Since pmc_core_slps0_display() and pmc_core_lpm_display() is responsible for dumping as well as displaying debug registers, there is no need for these two functions to be defined under CONFIG_DEBUG_FS. Hence, relocate these functions from under CONFIG_DEBUG_FS to above the block. Cc: Chen Zhou Cc: Andy Shevchenko Cc: David E. Box Signed-off-by: Gayatri Kammela Signed-off-by: Andy Shevchenko --- drivers/platform/x86/intel_pmc_core.c | 122 +++++++++++++++++----------------- 1 file changed, 61 insertions(+), 61 deletions(-) (limited to 'drivers/platform/x86/intel_pmc_core.c') diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c index f4a36fbabf4c..20b2f49726cf 100644 --- a/drivers/platform/x86/intel_pmc_core.c +++ b/drivers/platform/x86/intel_pmc_core.c @@ -612,6 +612,67 @@ static int pmc_core_check_read_lock_bit(void) return value & BIT(pmcdev->map->pm_read_disable_bit); } +static void pmc_core_slps0_display(struct pmc_dev *pmcdev, struct device *dev, + struct seq_file *s) +{ + const struct pmc_bit_map **maps = pmcdev->map->slps0_dbg_maps; + const struct pmc_bit_map *map; + int offset = pmcdev->map->slps0_dbg_offset; + u32 data; + + while (*maps) { + map = *maps; + data = pmc_core_reg_read(pmcdev, offset); + offset += 4; + while (map->name) { + if (dev) + dev_dbg(dev, "SLP_S0_DBG: %-32s\tState: %s\n", + map->name, + data & map->bit_mask ? "Yes" : "No"); + if (s) + seq_printf(s, "SLP_S0_DBG: %-32s\tState: %s\n", + map->name, + data & map->bit_mask ? "Yes" : "No"); + ++map; + } + ++maps; + } +} + +static void pmc_core_lpm_display(struct pmc_dev *pmcdev, struct device *dev, + struct seq_file *s, u32 offset, + const char *str, + const struct pmc_bit_map **maps) +{ + u32 lpm_regs[ARRAY_SIZE(tgl_lpm_maps)-1]; + int index, idx, len = 32, bit_mask; + + for (index = 0; tgl_lpm_maps[index]; index++) { + lpm_regs[index] = pmc_core_reg_read(pmcdev, offset); + offset += 4; + } + + for (idx = 0; maps[idx]; idx++) { + if (dev) + dev_dbg(dev, "\nLPM_%s_%d:\t0x%x\n", str, idx, + lpm_regs[idx]); + if (s) + seq_printf(s, "\nLPM_%s_%d:\t0x%x\n", str, idx, + lpm_regs[idx]); + for (index = 0; maps[idx][index].name && index < len; index++) { + bit_mask = maps[idx][index].bit_mask; + if (dev) + dev_dbg(dev, "%-30s %-30d\n", + maps[idx][index].name, + lpm_regs[idx] & bit_mask ? 1 : 0); + if (s) + seq_printf(s, "%-30s %-30d\n", + maps[idx][index].name, + lpm_regs[idx] & bit_mask ? 1 : 0); + } + } +} + #if IS_ENABLED(CONFIG_DEBUG_FS) static bool slps0_dbg_latch; @@ -844,33 +905,6 @@ out_unlock: mutex_unlock(&pmcdev->lock); } -static void pmc_core_slps0_display(struct pmc_dev *pmcdev, struct device *dev, - struct seq_file *s) -{ - const struct pmc_bit_map **maps = pmcdev->map->slps0_dbg_maps; - const struct pmc_bit_map *map; - int offset = pmcdev->map->slps0_dbg_offset; - u32 data; - - while (*maps) { - map = *maps; - data = pmc_core_reg_read(pmcdev, offset); - offset += 4; - while (map->name) { - if (dev) - dev_dbg(dev, "SLP_S0_DBG: %-32s\tState: %s\n", - map->name, - data & map->bit_mask ? "Yes" : "No"); - if (s) - seq_printf(s, "SLP_S0_DBG: %-32s\tState: %s\n", - map->name, - data & map->bit_mask ? "Yes" : "No"); - ++map; - } - ++maps; - } -} - static int pmc_core_slps0_dbg_show(struct seq_file *s, void *unused) { struct pmc_dev *pmcdev = s->private; @@ -974,40 +1008,6 @@ static int pmc_core_substate_res_show(struct seq_file *s, void *unused) } DEFINE_SHOW_ATTRIBUTE(pmc_core_substate_res); -static void pmc_core_lpm_display(struct pmc_dev *pmcdev, struct device *dev, - struct seq_file *s, u32 offset, - const char *str, - const struct pmc_bit_map **maps) -{ - u32 lpm_regs[ARRAY_SIZE(tgl_lpm_maps)-1]; - int index, idx, len = 32, bit_mask; - - for (index = 0; tgl_lpm_maps[index]; index++) { - lpm_regs[index] = pmc_core_reg_read(pmcdev, offset); - offset += 4; - } - - for (idx = 0; maps[idx]; idx++) { - if (dev) - dev_dbg(dev, "\nLPM_%s_%d:\t0x%x\n", str, idx, - lpm_regs[idx]); - if (s) - seq_printf(s, "\nLPM_%s_%d:\t0x%x\n", str, idx, - lpm_regs[idx]); - for (index = 0; maps[idx][index].name && index < len; index++) { - bit_mask = maps[idx][index].bit_mask; - if (dev) - dev_dbg(dev, "%-30s %-30d\n", - maps[idx][index].name, - lpm_regs[idx] & bit_mask ? 1 : 0); - if (s) - seq_printf(s, "%-30s %-30d\n", - maps[idx][index].name, - lpm_regs[idx] & bit_mask ? 1 : 0); - } - } -} - static int pmc_core_substate_sts_regs_show(struct seq_file *s, void *unused) { struct pmc_dev *pmcdev = s->private; -- cgit v1.2.3 From 08ec5020bd6cf0102ec92c00ed149d8b76ace5ee Mon Sep 17 00:00:00 2001 From: Gayatri Kammela Date: Thu, 27 Feb 2020 15:29:15 -0800 Subject: platform/x86: intel_pmc_core: Remove duplicate 'if' to create debugfs entry A debugfs entry for substate_live_status_registers is created only if the platform has sub-states, which requires the same condition to create substate_status_registers debugfs entry. Hence remove the redundant condition and re-use the existing one. Cc: Chen Zhou Cc: Andy Shevchenko Cc: David E. Box Signed-off-by: Gayatri Kammela Signed-off-by: Andy Shevchenko --- drivers/platform/x86/intel_pmc_core.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'drivers/platform/x86/intel_pmc_core.c') diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c index 20b2f49726cf..a36051c2a18c 100644 --- a/drivers/platform/x86/intel_pmc_core.c +++ b/drivers/platform/x86/intel_pmc_core.c @@ -1108,9 +1108,6 @@ static void pmc_core_dbgfs_register(struct pmc_dev *pmcdev) debugfs_create_file("substate_status_registers", 0444, pmcdev->dbgfs_dir, pmcdev, &pmc_core_substate_sts_regs_fops); - } - - if (pmcdev->map->lpm_status_offset) { debugfs_create_file("substate_live_status_registers", 0444, pmcdev->dbgfs_dir, pmcdev, &pmc_core_substate_l_sts_regs_fops); -- cgit v1.2.3 From 0e9c026f1b86a855cb9ab7aa270ff8db3c72015d Mon Sep 17 00:00:00 2001 From: Gayatri Kammela Date: Thu, 27 Feb 2020 15:29:16 -0800 Subject: platform/x86: intel_pmc_core: Add slp_s0_offset attribute back to tgl_reg_map If platforms such as Tiger Lake has sub-states of S0ix, then attributes such as slps0_dbg_offset become invalid. But slp_s0_offset is still valid as it is used to get the pmcdev_base_addr. Hence, add back slp_s0_offset and remove slps0_dbg_offset attributes. Cc: Chen Zhou Cc: Andy Shevchenko Cc: David E. Box Signed-off-by: Gayatri Kammela Signed-off-by: Andy Shevchenko --- drivers/platform/x86/intel_pmc_core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/platform/x86/intel_pmc_core.c') diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c index a36051c2a18c..986fe677d6fe 100644 --- a/drivers/platform/x86/intel_pmc_core.c +++ b/drivers/platform/x86/intel_pmc_core.c @@ -556,9 +556,9 @@ static const struct pmc_bit_map *tgl_lpm_maps[] = { static const struct pmc_reg_map tgl_reg_map = { .pfear_sts = ext_tgl_pfear_map, + .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET, .ltr_show_sts = cnp_ltr_show_map, .msr_sts = msr_map, - .slps0_dbg_offset = CNP_PMC_SLPS0_DBG_OFFSET, .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET, .regmap_length = CNP_PMC_MMIO_REG_LEN, .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A, -- cgit v1.2.3 From 267fc714cab797574a3a9df2074f05c3cdeb2511 Mon Sep 17 00:00:00 2001 From: Gayatri Kammela Date: Tue, 3 Mar 2020 13:28:08 -0800 Subject: platform/x86: intel_pmc_core: Make pmc_core_lpm_display() generic for platforms that support sub-states Currently pmc_core_lpm_display() uses an array of the struct pointers, i.e. tgl_lpm_maps for Tiger Lake directly to iterate through and to get the number of (live) status registers which is hard coded and can not be re-used for the future platforms that support sub-states. To maintain readability, make pmc_core_lpm_display() generic, so that it can be re-used for future platforms. Cc: Chen Zhou Cc: Andy Shevchenko Cc: David E. Box Suggested-by: Andy Shevchenko Signed-off-by: Gayatri Kammela Signed-off-by: Andy Shevchenko --- drivers/platform/x86/intel_pmc_core.c | 26 ++++++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-) (limited to 'drivers/platform/x86/intel_pmc_core.c') diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c index 986fe677d6fe..6ddb74d05ea6 100644 --- a/drivers/platform/x86/intel_pmc_core.c +++ b/drivers/platform/x86/intel_pmc_core.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include @@ -639,20 +640,35 @@ static void pmc_core_slps0_display(struct pmc_dev *pmcdev, struct device *dev, } } +static int pmc_core_lpm_get_arr_size(const struct pmc_bit_map **maps) +{ + int idx; + + for (idx = 0; maps[idx]; idx++) + ;/* Nothing */ + + return idx; +} + static void pmc_core_lpm_display(struct pmc_dev *pmcdev, struct device *dev, struct seq_file *s, u32 offset, const char *str, const struct pmc_bit_map **maps) { - u32 lpm_regs[ARRAY_SIZE(tgl_lpm_maps)-1]; - int index, idx, len = 32, bit_mask; + int index, idx, len = 32, bit_mask, arr_size; + u32 *lpm_regs; + + arr_size = pmc_core_lpm_get_arr_size(maps); + lpm_regs = kmalloc_array(arr_size, sizeof(*lpm_regs), GFP_KERNEL); + if (!lpm_regs) + return; - for (index = 0; tgl_lpm_maps[index]; index++) { + for (index = 0; index < arr_size; index++) { lpm_regs[index] = pmc_core_reg_read(pmcdev, offset); offset += 4; } - for (idx = 0; maps[idx]; idx++) { + for (idx = 0; idx < arr_size; idx++) { if (dev) dev_dbg(dev, "\nLPM_%s_%d:\t0x%x\n", str, idx, lpm_regs[idx]); @@ -671,6 +687,8 @@ static void pmc_core_lpm_display(struct pmc_dev *pmcdev, struct device *dev, lpm_regs[idx] & bit_mask ? 1 : 0); } } + + kfree(lpm_regs); } #if IS_ENABLED(CONFIG_DEBUG_FS) -- cgit v1.2.3 From c61b693c9a032991f34cc4034b466d7807fd61ab Mon Sep 17 00:00:00 2001 From: Gayatri Kammela Date: Sun, 1 Mar 2020 12:44:25 -0800 Subject: platform/x86: intel_pmc_core: Make pmc_core_substate_res_show() generic Currently pmc_core_substate_res_show() uses array of char pointers i.e., lpm_modes for Tiger Lake directly to iterate through and to get the number of low power modes which is hardcoded and cannot be re-used for future platforms that support sub-states. To maintain readability, make pmc_core_substate_res_show() generic, so that it can re-used for future platforms. Cc: Chen Zhou Cc: Andy Shevchenko Cc: David E. Box Signed-off-by: Gayatri Kammela Signed-off-by: Andy Shevchenko --- drivers/platform/x86/intel_pmc_core.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/platform/x86/intel_pmc_core.c') diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c index 6ddb74d05ea6..d265cd5b1f45 100644 --- a/drivers/platform/x86/intel_pmc_core.c +++ b/drivers/platform/x86/intel_pmc_core.c @@ -567,6 +567,7 @@ static const struct pmc_reg_map tgl_reg_map = { .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET, .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT, .ltr_ignore_max = TGL_NUM_IP_IGN_ALLOWED, + .lpm_modes = tgl_lpm_modes, .lpm_en_offset = TGL_LPM_EN_OFFSET, .lpm_residency_offset = TGL_LPM_RESIDENCY_OFFSET, .lpm_sts = tgl_lpm_maps, @@ -1009,6 +1010,7 @@ DEFINE_SHOW_ATTRIBUTE(pmc_core_ltr); static int pmc_core_substate_res_show(struct seq_file *s, void *unused) { struct pmc_dev *pmcdev = s->private; + const char **lpm_modes = pmcdev->map->lpm_modes; u32 offset = pmcdev->map->lpm_residency_offset; u32 lpm_en; int index; -- cgit v1.2.3