From 9a6a644096a1066c2ef5c47db0db79ac72af7967 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= Date: Fri, 14 Jun 2019 14:37:49 -0700 Subject: drm/i915/ehl: Add missing VECS engine MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit EHL can have up to one VECS(video enhancement) engine, so add it to the device_info. BSpec: 29152 Cc: Rodrigo Vivi Cc: Bob Paauwe Cc: Matt Roper Cc: Clint Taylor Signed-off-by: José Roberto de Souza Reviewed-by: Matt Roper Link: https://patchwork.freedesktop.org/patch/msgid/20190614213749.15870-1-jose.souza@intel.com --- drivers/gpu/drm/i915/i915_pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/i915/i915_pci.c') diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 6c9f46fc3e12..94b588e0a1dd 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -761,7 +761,7 @@ static const struct intel_device_info intel_elkhartlake_info = { GEN11_FEATURES, PLATFORM(INTEL_ELKHARTLAKE), .require_force_probe = 1, - .engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0), + .engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0), .ppgtt_size = 36, }; -- cgit v1.2.3 From abd3a0fe040d51fc2943855169558b4b0b3311c6 Mon Sep 17 00:00:00 2001 From: Daniele Ceraolo Spurio Date: Thu, 11 Jul 2019 10:30:56 -0700 Subject: drm/i915/tgl: add initial Tiger Lake definitions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Tiger Lake is a Intel® Processor containing Intel® HD Graphics. This is just an initial Tiger Lake definition. PCI IDs, generic support and new features coming in following patches. v2 (Lucas): - Remove modular FIA - feature will be re-introduced in future Cc: Joonas Lahtinen Cc: Rodrigo Vivi Signed-off-by: Daniele Ceraolo Spurio Signed-off-by: Lucas De Marchi Reviewed-by: Anusha Srivatsa Link: https://patchwork.freedesktop.org/patch/msgid/20190711173115.28296-3-lucas.demarchi@intel.com --- drivers/gpu/drm/i915/i915_pci.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'drivers/gpu/drm/i915/i915_pci.c') diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 94b588e0a1dd..da926485845d 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -765,6 +765,35 @@ static const struct intel_device_info intel_elkhartlake_info = { .ppgtt_size = 36, }; +#define GEN12_FEATURES \ + GEN11_FEATURES, \ + GEN(12), \ + .pipe_offsets = { \ + [TRANSCODER_A] = PIPE_A_OFFSET, \ + [TRANSCODER_B] = PIPE_B_OFFSET, \ + [TRANSCODER_C] = PIPE_C_OFFSET, \ + [TRANSCODER_D] = PIPE_D_OFFSET, \ + [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ + [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ + }, \ + .trans_offsets = { \ + [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ + [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ + [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ + [TRANSCODER_D] = TRANSCODER_D_OFFSET, \ + [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ + [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ + } + +static const struct intel_device_info intel_tigerlake_12_info = { + GEN12_FEATURES, + PLATFORM(INTEL_TIGERLAKE), + .num_pipes = 4, + .require_force_probe = 1, + .engine_mask = + BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), +}; + #undef GEN #undef PLATFORM -- cgit v1.2.3 From 9747f0c2fb9e1a6d7c907d34a373924c84093afa Mon Sep 17 00:00:00 2001 From: Lucas De Marchi Date: Thu, 11 Jul 2019 10:30:59 -0700 Subject: drm/i915/tgl: Add TGL PCI IDs Current list of PCI IDs for Tiger Lake. Cc: Rodrigo Vivi Signed-off-by: Lucas De Marchi Reviewed-by: Rodrigo Vivi Reviewed-by: Mika Kahola Link: https://patchwork.freedesktop.org/patch/msgid/20190711173115.28296-6-lucas.demarchi@intel.com --- drivers/gpu/drm/i915/i915_pci.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/drm/i915/i915_pci.c') diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index da926485845d..e83c94cf2744 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -865,6 +865,7 @@ static const struct pci_device_id pciidlist[] = { INTEL_CNL_IDS(&intel_cannonlake_info), INTEL_ICL_11_IDS(&intel_icelake_11_info), INTEL_EHL_IDS(&intel_elkhartlake_info), + INTEL_TGL_12_IDS(&intel_tigerlake_12_info), {0, 0, 0} }; MODULE_DEVICE_TABLE(pci, pciidlist); -- cgit v1.2.3 From b01558e56f84866dcad5f3f99819ec560d639f09 Mon Sep 17 00:00:00 2001 From: Janusz Krzysztofik Date: Fri, 12 Jul 2019 13:24:26 +0200 Subject: drm/i915: Rename "_load"/"_unload" to match PCI entry points Current names of i915_driver_load/unload() functions originate in legacy DRM stubs. Reduce nomenclature ambiguity by renaming them to match their current use as helpers called from PCI entry points. Suggested by: Chris Wilson Signed-off-by: Janusz Krzysztofik Reviewed-by: Chris Wilson Reviewed-by: Joonas Lahtinen Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20190712112429.740-3-janusz.krzysztofik@linux.intel.com --- drivers/gpu/drm/i915/i915_pci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/i915/i915_pci.c') diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index e83c94cf2744..49558727b5f3 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -878,7 +878,7 @@ static void i915_pci_remove(struct pci_dev *pdev) if (!dev) /* driver load aborted, nothing to cleanup */ return; - i915_driver_unload(dev); + i915_driver_remove(dev); drm_dev_put(dev); pci_set_drvdata(pdev, NULL); @@ -953,7 +953,7 @@ static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) if (vga_switcheroo_client_probe_defer(pdev)) return -EPROBE_DEFER; - err = i915_driver_load(pdev, ent); + err = i915_driver_probe(pdev, ent); if (err) return err; -- cgit v1.2.3 From f2db53f14d3d1cde1d4c3b5b5aaba556c953f2f5 Mon Sep 17 00:00:00 2001 From: Janusz Krzysztofik Date: Fri, 12 Jul 2019 13:24:27 +0200 Subject: drm/i915: Replace "_load" with "_probe" consequently Use the "_probe" nomenclature not only in i915_driver_probe() helper name but also in other related function / variable names for consistency. Only the userspace exposed name of a related module parameter is left untouched. Signed-off-by: Janusz Krzysztofik Reviewed-by: Chris Wilson Reviewed-by: Joonas Lahtinen Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20190712112429.740-4-janusz.krzysztofik@linux.intel.com --- drivers/gpu/drm/i915/i915_pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/i915/i915_pci.c') diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 49558727b5f3..95763ad92287 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -957,7 +957,7 @@ static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) if (err) return err; - if (i915_inject_load_failure()) { + if (i915_inject_probe_failure()) { i915_pci_remove(pdev); return -ENODEV; } -- cgit v1.2.3 From 139ab811511ce46d29dd0a2a861d0ac0f04d2fe6 Mon Sep 17 00:00:00 2001 From: Lucas De Marchi Date: Thu, 11 Jul 2019 22:57:06 -0700 Subject: drm/i915/tgl: add modular FIA to device info Tiger Lake has modular FIA bit indicating if we are using it, so add to the device info. Signed-off-by: Lucas De Marchi Reviewed-by: Stuart Summers Link: https://patchwork.freedesktop.org/patch/msgid/20190712055706.12143-3-lucas.demarchi@intel.com --- drivers/gpu/drm/i915/i915_pci.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/drm/i915/i915_pci.c') diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 95763ad92287..40076ba431d4 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -790,6 +790,7 @@ static const struct intel_device_info intel_tigerlake_12_info = { PLATFORM(INTEL_TIGERLAKE), .num_pipes = 4, .require_force_probe = 1, + .display.has_modular_fia = 1, .engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), }; -- cgit v1.2.3 From 702668e606c0618fd62c7a5d051c9faee256c049 Mon Sep 17 00:00:00 2001 From: Daniele Ceraolo Spurio Date: Wed, 24 Jul 2019 17:18:06 -0700 Subject: drm/i915/uc: Unify uC platform check We have several HAS_* checks for GuC and HuC but we mostly use HAS_GUC and HAS_HUC, with only 1 exception. Since our HW always has either both uC or neither of them, just replace all the checks with a unified HAS_UC. v2: use HAS_GT_UC (Michal) v3: fix comment (Michal) Signed-off-by: Daniele Ceraolo Spurio Cc: Michal Wajdeczko Acked-by: Chris Wilson Reviewed-by: Michal Wajdeczko Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20190725001813.4740-2-daniele.ceraolospurio@intel.com --- drivers/gpu/drm/i915/i915_pci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/i915/i915_pci.c') diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 40076ba431d4..bd9211b3d76e 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -595,7 +595,7 @@ static const struct intel_device_info intel_cherryview_info = { GEN9_DEFAULT_PAGE_SIZES, \ .has_logical_ring_preemption = 1, \ .display.has_csr = 1, \ - .has_guc = 1, \ + .has_gt_uc = 1, \ .display.has_ipc = 1, \ .ddb_size = 896 @@ -647,7 +647,7 @@ static const struct intel_device_info intel_skylake_gt4_info = { .display.has_dp_mst = 1, \ .has_logical_ring_contexts = 1, \ .has_logical_ring_preemption = 1, \ - .has_guc = 1, \ + .has_gt_uc = 1, \ .ppgtt_type = INTEL_PPGTT_FULL, \ .ppgtt_size = 48, \ .has_reset_engine = 1, \ -- cgit v1.2.3 From a7a7a0e6ebde34e05793d390cc9303e06e8f8dd1 Mon Sep 17 00:00:00 2001 From: Michel Thierry Date: Tue, 30 Jul 2019 11:04:06 -0700 Subject: drm/i915/tgl: Tigerlake only has global MOCS registers Until Icelake, each engine had its own set of 64 MOCS registers. In order to simplify, Tigerlake moves to only 64 Global MOCS registers, which are no longer part of the engine context. Since these registers are now global, they also only need to be initialized once. >From Gen12 onwards, MOCS must specify the target cache (3:2) and LRU management (5:4) fields and cannot be programmed to 'use the value from Private PAT', because these fields are no longer part of the PPAT. Also cacheability control (1:0) field has changed, 00 no longer means 'use controls from page table', but uncacheable (UC). v2 (Lucas): - Move the changes to the fault registers to a separate commit - the old ones overlap with the range used by the new global MOCS (requested by Daniele) v3 (Lucas): - Clarify comment about setting the unused entries to the same value of index 0, that is the invalid entry (requested by Daniele) - Move changes to DONE_REG and ERROR_GEN6 to a separate commit (requested by Daniele) Cc: Daniele Ceraolo Spurio Signed-off-by: Michel Thierry Signed-off-by: Tvrtko Ursulin Signed-off-by: Lucas De Marchi Reviewed-by: Tomasz Lis Link: https://patchwork.freedesktop.org/patch/msgid/20190730180407.5993-5-lucas.demarchi@intel.com --- drivers/gpu/drm/i915/i915_pci.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/i915/i915_pci.c') diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index bd9211b3d76e..a7e1cde4a6d9 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -783,7 +783,8 @@ static const struct intel_device_info intel_elkhartlake_info = { [TRANSCODER_D] = TRANSCODER_D_OFFSET, \ [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ - } + }, \ + .has_global_mocs = 1 static const struct intel_device_info intel_tigerlake_12_info = { GEN12_FEATURES, -- cgit v1.2.3 From 50d84418f58699272a9220f9447bf89f0440c671 Mon Sep 17 00:00:00 2001 From: Michal Wajdeczko Date: Fri, 2 Aug 2019 18:40:50 +0000 Subject: drm/i915: Add i915 to i915_inject_probe_failure With i915 added to i915_inject_probe_failure we can use dedicated printk when injecting artificial load failure. Also make this function look like other i915 functions that return error code and make it more flexible to return any provided error code instead of previously assumed -ENODEV. Signed-off-by: Michal Wajdeczko Cc: Daniele Ceraolo Spurio Cc: Chris Wilson Reviewed-by: Chris Wilson Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20190802184055.31988-2-michal.wajdeczko@intel.com --- drivers/gpu/drm/i915/i915_pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/i915/i915_pci.c') diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index a7e1cde4a6d9..20e562ced8cc 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -959,7 +959,7 @@ static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) if (err) return err; - if (i915_inject_probe_failure()) { + if (i915_inject_probe_failure(to_i915(pci_get_drvdata(pdev)))) { i915_pci_remove(pdev); return -ENODEV; } -- cgit v1.2.3 From 361f9dc2436812cbcf727fe73d0a4c11ca895fbb Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Tue, 6 Aug 2019 08:42:19 +0100 Subject: drm/i915: Use drm_i915_private directly from drv_get_drvdata() As we store a pointer to i915 in the drvdata field (as the pointer is both an alias to the drm_device and drm_i915_private), we can use the stored pointer directly as the i915 device. v2: Store and use i915 inside drv_get_drvdata() v3: Only expect i915 inside drv_get_drvdata() so drop the assumed i915/drm equivalence. Signed-off-by: Chris Wilson Cc: Andi Shyti Reviewed-by: Andi Shyti Link: https://patchwork.freedesktop.org/patch/msgid/20190806074219.11043-1-chris@chris-wilson.co.uk --- drivers/gpu/drm/i915/i915_pci.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'drivers/gpu/drm/i915/i915_pci.c') diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 20e562ced8cc..1febda2a90e7 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -874,16 +874,16 @@ MODULE_DEVICE_TABLE(pci, pciidlist); static void i915_pci_remove(struct pci_dev *pdev) { - struct drm_device *dev; + struct drm_i915_private *i915; - dev = pci_get_drvdata(pdev); - if (!dev) /* driver load aborted, nothing to cleanup */ + i915 = pci_get_drvdata(pdev); + if (!i915) /* driver load aborted, nothing to cleanup */ return; - i915_driver_remove(dev); - drm_dev_put(dev); - + i915_driver_remove(i915); pci_set_drvdata(pdev, NULL); + + drm_dev_put(&i915->drm); } /* is device_id present in comma separated list of ids */ @@ -959,7 +959,7 @@ static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) if (err) return err; - if (i915_inject_probe_failure(to_i915(pci_get_drvdata(pdev)))) { + if (i915_inject_probe_failure(pci_get_drvdata(pdev))) { i915_pci_remove(pdev); return -ENODEV; } -- cgit v1.2.3 From aaa914cd1c6332950523c942988a2ccd7cc2f7d9 Mon Sep 17 00:00:00 2001 From: Matthew Auld Date: Fri, 9 Aug 2019 20:34:56 +0100 Subject: drm/i915/gtt: disable 2M pages for pre-gen11 We currently disable THP(Transparent-Huge-Pages) for our shmem objects due to a performance regression with read BW in some internal benchmarks. Given that this is our main source of 2M pages, there really isn't much point in enabling 2M GTT pages, especially as that comes at the cost of disabling the GTT cache. However from gen11 it looks like we should hopefully see the HW issue resolved. Given this opt for only enabling 2M GTT pages from gen11 onwards. Signed-off-by: Matthew Auld Cc: Joonas Lahtinen Cc: Chris Wilson Reviewed-by: Chris Wilson Signed-off-by: Chris Wilson Link: https://patchwork.freedesktop.org/patch/msgid/20190809193456.3836-2-matthew.auld@intel.com --- drivers/gpu/drm/i915/i915_pci.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/drm/i915/i915_pci.c') diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 1febda2a90e7..1974e4c78a43 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -522,8 +522,6 @@ static const struct intel_device_info intel_haswell_gt3_info = { #define GEN8_FEATURES \ G75_FEATURES, \ GEN(8), \ - .page_sizes = I915_GTT_PAGE_SIZE_4K | \ - I915_GTT_PAGE_SIZE_2M, \ .has_logical_ring_contexts = 1, \ .ppgtt_type = INTEL_PPGTT_FULL, \ .ppgtt_size = 48, \ @@ -586,8 +584,7 @@ static const struct intel_device_info intel_cherryview_info = { #define GEN9_DEFAULT_PAGE_SIZES \ .page_sizes = I915_GTT_PAGE_SIZE_4K | \ - I915_GTT_PAGE_SIZE_64K | \ - I915_GTT_PAGE_SIZE_2M + I915_GTT_PAGE_SIZE_64K #define GEN9_FEATURES \ GEN8_FEATURES, \ @@ -727,8 +724,14 @@ static const struct intel_device_info intel_cannonlake_info = { .gt = 2, }; +#define GEN11_DEFAULT_PAGE_SIZES \ + .page_sizes = I915_GTT_PAGE_SIZE_4K | \ + I915_GTT_PAGE_SIZE_64K | \ + I915_GTT_PAGE_SIZE_2M + #define GEN11_FEATURES \ GEN10_FEATURES, \ + GEN11_DEFAULT_PAGE_SIZES, \ .pipe_offsets = { \ [TRANSCODER_A] = PIPE_A_OFFSET, \ [TRANSCODER_B] = PIPE_B_OFFSET, \ -- cgit v1.2.3