From 5f0601c47c336ae75aec9ed308b6c4428c7d179b Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Tue, 14 Sep 2021 14:52:01 +0800 Subject: clk: imx: Update the pllv4 to support imx8ulp The PLLs used on i.MX8ULP is mostly the same as on i.MX7ULP, except the PLL register offset is changed. Change the PLLv4 driver for code reuse on i.MX7ULP and i.MX8ULP. Signed-off-by: Jacky Bai Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20210914065208.3582128-3-ping.bai@nxp.com Signed-off-by: Abel Vesa --- drivers/clk/imx/clk-imx7ulp.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/clk/imx/clk-imx7ulp.c') diff --git a/drivers/clk/imx/clk-imx7ulp.c b/drivers/clk/imx/clk-imx7ulp.c index 779e09105da7..ba50d6db8097 100644 --- a/drivers/clk/imx/clk-imx7ulp.c +++ b/drivers/clk/imx/clk-imx7ulp.c @@ -78,8 +78,8 @@ static void __init imx7ulp_clk_scg1_init(struct device_node *np) hws[IMX7ULP_CLK_SPLL_PRE_DIV] = imx_clk_hw_divider_flags("spll_pre_div", "spll_pre_sel", base + 0x608, 8, 3, CLK_SET_RATE_GATE); /* name parent_name base */ - hws[IMX7ULP_CLK_APLL] = imx_clk_hw_pllv4("apll", "apll_pre_div", base + 0x500); - hws[IMX7ULP_CLK_SPLL] = imx_clk_hw_pllv4("spll", "spll_pre_div", base + 0x600); + hws[IMX7ULP_CLK_APLL] = imx_clk_hw_pllv4(IMX_PLLV4_IMX7ULP, "apll", "apll_pre_div", base + 0x500); + hws[IMX7ULP_CLK_SPLL] = imx_clk_hw_pllv4(IMX_PLLV4_IMX7ULP, "spll", "spll_pre_div", base + 0x600); /* APLL PFDs */ hws[IMX7ULP_CLK_APLL_PFD0] = imx_clk_hw_pfdv2("apll_pfd0", "apll", base + 0x50c, 0); -- cgit v1.2.3