From 1c98398662c9b4e2f03f64344f83dd6cb14e0420 Mon Sep 17 00:00:00 2001 From: Yonghong Song <ysong@broadcom.com> Date: Tue, 29 Apr 2014 20:07:53 +0530 Subject: MIPS: Netlogic: Add support for XLP5XX Add support for the XLP5XX processor which is an 8 core variant of the XLP9XX. Add XLP5XX cases to code which earlier handled XLP9XX. Signed-off-by: Yonghong Song <ysong@broadcom.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6871/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> --- arch/mips/netlogic/common/reset.S | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/mips/netlogic/common/reset.S') diff --git a/arch/mips/netlogic/common/reset.S b/arch/mips/netlogic/common/reset.S index 5b60b469da15..701c4bcb9e47 100644 --- a/arch/mips/netlogic/common/reset.S +++ b/arch/mips/netlogic/common/reset.S @@ -177,6 +177,10 @@ FEXPORT(nlm_reset_entry) beq t0, t1, 2f /* does not need to set coherent */ nop + li t1, 0x1300 /* XLP 5xx */ + beq t0, t1, 2f /* does not need to set coherent */ + nop + /* set bit in SYS coherent register for the core */ mfc0 t0, CP0_EBASE, 1 mfc0 t1, CP0_EBASE, 1 -- cgit v1.2.3