From 553b085c2075f6a4a2591108554f830fa61e881f Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 7 Mar 2018 21:36:19 +0100 Subject: arch: remove m32r port The Mitsubishi/Renesas m32r architecture has been around for many years, but the Linux port has been obsolete for a very long time as well, with the last significant updates done for linux-2.6.14. While some m32r microcontrollers are still being marketed by Renesas, those are apparently no longer possible to support, mainly due to the lack of an external memory interface. Hirokazu Takata was the maintainer until the architecture got marked Orphaned in 2014. Link: http://www.linux-m32r.org/ Link: https://www.renesas.com/en-eu/products/microcontrollers-microprocessors/m32r.html Cc: Hirokazu Takata Signed-off-by: Arnd Bergmann --- arch/m32r/include/asm/cachectl.h | 27 --------------------------- 1 file changed, 27 deletions(-) delete mode 100644 arch/m32r/include/asm/cachectl.h (limited to 'arch/m32r/include/asm/cachectl.h') diff --git a/arch/m32r/include/asm/cachectl.h b/arch/m32r/include/asm/cachectl.h deleted file mode 100644 index 12f73f6c1759..000000000000 --- a/arch/m32r/include/asm/cachectl.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * cachectl.h -- defines for M32R cache control system calls - * - * Copyright (C) 2003 by Kazuhiro Inaoka - */ -#ifndef __ASM_M32R_CACHECTL -#define __ASM_M32R_CACHECTL - -/* - * Options for cacheflush system call - * - * cacheflush() is currently fluch_cache_all(). - */ -#define ICACHE (1<<0) /* flush instruction cache */ -#define DCACHE (1<<1) /* writeback and flush data cache */ -#define BCACHE (ICACHE|DCACHE) /* flush both caches */ - -/* - * Caching modes for the cachectl(2) call - * - * cachectl(2) is currently not supported and returns ENOSYS. - */ -#define CACHEABLE 0 /* make pages cacheable */ -#define UNCACHEABLE 1 /* make pages uncacheable */ - -#endif /* __ASM_M32R_CACHECTL */ -- cgit v1.2.3