From 8c7e955fac07ee11c76ddf2330587fe083fab1a2 Mon Sep 17 00:00:00 2001 From: Christian Bruel Date: Mon, 30 Sep 2024 19:08:43 +0200 Subject: dt-bindings: phy: Add STM32MP25 COMBOPHY bindings Document the bindings for STM32 COMBOPHY interface, used to support the PCIe and USB3 stm32mp25 drivers. Following entries can be used to tune caracterisation parameters - st,output-micro-ohms and st,output-vswing-microvolt bindings entries to tune the impedance and voltage swing using discrete simulation results - st,rx-equalizer register to set the internal rx equalizer filter value. Reviewed-by: Rob Herring (Arm) Signed-off-by: Christian Bruel Link: https://lore.kernel.org/r/20240930170847.948779-2-christian.bruel@foss.st.com Signed-off-by: Vinod Koul --- .../bindings/phy/st,stm32mp25-combophy.yaml | 119 +++++++++++++++++++++ 1 file changed, 119 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/st,stm32mp25-combophy.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/st,stm32mp25-combophy.yaml b/Documentation/devicetree/bindings/phy/st,stm32mp25-combophy.yaml new file mode 100644 index 000000000000..a2e82c0bb56b --- /dev/null +++ b/Documentation/devicetree/bindings/phy/st,stm32mp25-combophy.yaml @@ -0,0 +1,119 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/st,stm32mp25-combophy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32MP25 USB3/PCIe COMBOPHY + +maintainers: + - Christian Bruel + +description: + Single lane PHY shared (exclusive) between the USB3 and PCIe controllers. + Supports 5Gbit/s for USB3 and PCIe gen2 or 2.5Gbit/s for PCIe gen1. + +properties: + compatible: + const: st,stm32mp25-combophy + + reg: + maxItems: 1 + + "#phy-cells": + const: 1 + + clocks: + minItems: 2 + items: + - description: apb Bus clock mandatory to access registers. + - description: ker Internal RCC reference clock for USB3 or PCIe + - description: pad Optional on board clock input for PCIe only. Typically an + external 100Mhz oscillator wired on dedicated CLKIN pad. Used as reference + clock input instead of the ker + + clock-names: + minItems: 2 + items: + - const: apb + - const: ker + - const: pad + + resets: + maxItems: 1 + + reset-names: + const: phy + + power-domains: + maxItems: 1 + + wakeup-source: true + + interrupts: + maxItems: 1 + description: interrupt used for wakeup + + access-controllers: + maxItems: 1 + description: Phandle to the rifsc device to check access right. + + st,ssc-on: + $ref: /schemas/types.yaml#/definitions/flag + description: + A property whose presence indicates that the Spread Spectrum Clocking is active. + + st,rx-equalizer: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 7 + default: 2 + description: + A 3 bit value to tune the RX fixed equalizer setting for optimal eye compliance + + st,output-micro-ohms: + minimum: 3999000 + maximum: 6090000 + default: 4968000 + description: + A value property to tune the Single Ended Output Impedance, simulations results + at 25C for a VDDP=0.8V. The hardware accepts discrete values in this range. + + st,output-vswing-microvolt: + minimum: 442000 + maximum: 803000 + default: 803000 + description: + A value property in microvolt to tune the Single Ended Output Voltage Swing to change the + Vlo, Vhi for a VDDP = 0.8V. The hardware accepts discrete values in this range. + +required: + - compatible + - reg + - "#phy-cells" + - clocks + - clock-names + - resets + - reset-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + + phy@480c0000 { + compatible = "st,stm32mp25-combophy"; + reg = <0x480c0000 0x1000>; + #phy-cells = <1>; + clocks = <&rcc CK_BUS_USB3PCIEPHY>, <&rcc CK_KER_USB3PCIEPHY>; + clock-names = "apb", "ker"; + resets = <&rcc USB3PCIEPHY_R>; + reset-names = "phy"; + access-controllers = <&rifsc 67>; + power-domains = <&CLUSTER_PD>; + wakeup-source; + interrupts-extended = <&exti1 45 IRQ_TYPE_EDGE_FALLING>; + }; -- cgit v1.2.3 From bbcc9e2bde693ec3fc6aab650abaf748eb9f38f9 Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Mon, 30 Sep 2024 15:21:45 +0530 Subject: dt-bindings: phy: cadence-sierra: Allow PHY types QSGMII and SGMII The Sierra SERDES can be configured for QSGMII and SGMII protocols. Hence, update the bindings to treat "PHY_TYPE_QSGMII" and "PHY_TYPE_SGMII" as valid values for the "cdns,phy-type" property. Signed-off-by: Siddharth Vadapalli Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20240930095145.3004053-1-s-vadapalli@ti.com Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml index 37f028f7a095..137ac5703853 100644 --- a/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml +++ b/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml @@ -96,7 +96,7 @@ patternProperties: Specifies the type of PHY for which the group of PHY lanes is used. Refer include/dt-bindings/phy/phy.h. Constants from the header should be used. $ref: /schemas/types.yaml#/definitions/uint32 - enum: [2, 4] + enum: [2, 4, 8, 9] cdns,num-lanes: description: -- cgit v1.2.3 From 3624fa00ae76be6a93d46071db12bf9218090cb4 Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Thu, 10 Oct 2024 01:23:45 +0530 Subject: dt-bindings: usb: qcom,dwc3: Add QCS8300 to USB DWC3 bindings Update dt-bindings to add QCS8300 to USB DWC3 controller list. The second controller of QCS8300 is High speed only capable and doesn't have ss_phy_irq. Signed-off-by: Krishna Kurapati Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20241009195348.2649368-2-quic_kriskura@quicinc.com Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/usb/qcom,dwc3.yaml | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml index 18758efb8d29..f7be05641930 100644 --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml @@ -26,6 +26,7 @@ properties: - qcom,msm8998-dwc3 - qcom,qcm2290-dwc3 - qcom,qcs404-dwc3 + - qcom,qcs8300-dwc3 - qcom,qdu1000-dwc3 - qcom,sa8775p-dwc3 - qcom,sc7180-dwc3 @@ -201,6 +202,7 @@ allOf: - qcom,msm8953-dwc3 - qcom,msm8996-dwc3 - qcom,msm8998-dwc3 + - qcom,qcs8300-dwc3 - qcom,sa8775p-dwc3 - qcom,sc7180-dwc3 - qcom,sc7280-dwc3 @@ -465,6 +467,7 @@ allOf: - qcom,ipq4019-dwc3 - qcom,ipq8064-dwc3 - qcom,msm8994-dwc3 + - qcom,qcs8300-dwc3 - qcom,qdu1000-dwc3 - qcom,sa8775p-dwc3 - qcom,sc7180-dwc3 @@ -490,6 +493,7 @@ allOf: minItems: 4 maxItems: 5 interrupt-names: + minItems: 4 items: - const: pwr_event - const: hs_phy_irq -- cgit v1.2.3 From c5a3519eae7c491646a87c4861e91f1a1a9f461e Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Thu, 10 Oct 2024 01:23:46 +0530 Subject: dt-bindings: phy: qcom,usb-snps-femto-v2: Add bindings for QCS8300 Update dt-bindings to add QCS8300 to USB2 SNPS Femto Phy list. Signed-off-by: Krishna Kurapati Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20241009195348.2649368-3-quic_kriskura@quicinc.com Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/qcom,usb-snps-femto-v2.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/qcom,usb-snps-femto-v2.yaml b/Documentation/devicetree/bindings/phy/qcom,usb-snps-femto-v2.yaml index 519c2b403f66..661759b25064 100644 --- a/Documentation/devicetree/bindings/phy/qcom,usb-snps-femto-v2.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,usb-snps-femto-v2.yaml @@ -22,6 +22,7 @@ properties: - const: qcom,usb-snps-hs-5nm-phy - items: - enum: + - qcom,qcs8300-usb-hs-phy - qcom,qdu1000-usb-hs-phy - qcom,sc7280-usb-hs-phy - qcom,sc8180x-usb-hs-phy -- cgit v1.2.3 From c2b174209bbb3341444c899f0a06f21eb953b1f0 Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Thu, 10 Oct 2024 01:23:47 +0530 Subject: dt-bindings: phy: qcom,sc8280xp-qmp-usb3-uni: Add QCS8300 compatible Update dt-bindings to add QCS8300 to QMP Uni Phy list. Signed-off-by: Krishna Kurapati Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20241009195348.2649368-4-quic_kriskura@quicinc.com Signed-off-by: Vinod Koul --- .../devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml index 0e0b6cae07bc..baf5134ea3d8 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml @@ -20,6 +20,7 @@ properties: - qcom,ipq8074-qmp-usb3-phy - qcom,ipq9574-qmp-usb3-phy - qcom,msm8996-qmp-usb3-phy + - qcom,qcs8300-qmp-usb3-uni-phy - qcom,qdu1000-qmp-usb3-uni-phy - qcom,sa8775p-qmp-usb3-uni-phy - qcom,sc8180x-qmp-usb3-uni-phy @@ -111,6 +112,7 @@ allOf: compatible: contains: enum: + - qcom,qcs8300-qmp-usb3-uni-phy - qcom,qdu1000-qmp-usb3-uni-phy - qcom,sa8775p-qmp-usb3-uni-phy - qcom,sc8180x-qmp-usb3-uni-phy -- cgit v1.2.3 From 03b9d469e03d9ab1a991d8562e2d5e6c0e57558a Mon Sep 17 00:00:00 2001 From: Yijie Yang Date: Thu, 17 Oct 2024 17:52:38 +0800 Subject: dt-bindings: phy: describe the Qualcomm SGMII PHY Describe the SGMII/SerDes PHY present on the qcs8300 platforms. Since qcs8300 shares the same SerDes as sa8775p, so it fallback to the compatible. Signed-off-by: Yijie Yang Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20241017-schema-v2-2-2320f68dc126@quicinc.com Signed-off-by: Vinod Koul --- .../devicetree/bindings/phy/qcom,sa8775p-dwmac-sgmii-phy.yaml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/qcom,sa8775p-dwmac-sgmii-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sa8775p-dwmac-sgmii-phy.yaml index b9107759b2a5..90fc8c039219 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sa8775p-dwmac-sgmii-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sa8775p-dwmac-sgmii-phy.yaml @@ -15,7 +15,12 @@ description: properties: compatible: - const: qcom,sa8775p-dwmac-sgmii-phy + oneOf: + - items: + - enum: + - qcom,qcs8300-dwmac-sgmii-phy + - const: qcom,sa8775p-dwmac-sgmii-phy + - const: qcom,sa8775p-dwmac-sgmii-phy reg: items: -- cgit v1.2.3 From 6a612c86c8a5805c85fde359aa9c8aac6d5cba7a Mon Sep 17 00:00:00 2001 From: Sayali Lokhande Date: Thu, 17 Oct 2024 12:22:57 +0800 Subject: dt-bindings: phy: Add QMP UFS PHY comptible for QCS615 Document the QMP UFS PHY compatible for Qualcomm QCS615 to support physical layer functionality for UFS found on the SoC. Use fallback to indicate the compatibility of the QMP UFS PHY on the QCS615 with that on the SM6115. Signed-off-by: Sayali Lokhande Co-developed-by: Xin Liu Signed-off-by: Xin Liu Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20241017042300.872963-2-quic_liuxin@quicinc.com Signed-off-by: Vinod Koul --- .../bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml | 45 ++++++++++++---------- 1 file changed, 25 insertions(+), 20 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml index f9cfbd0b2de6..a93d64d1c55b 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml @@ -15,26 +15,31 @@ description: properties: compatible: - enum: - - qcom,msm8996-qmp-ufs-phy - - qcom,msm8998-qmp-ufs-phy - - qcom,sa8775p-qmp-ufs-phy - - qcom,sc7180-qmp-ufs-phy - - qcom,sc7280-qmp-ufs-phy - - qcom,sc8180x-qmp-ufs-phy - - qcom,sc8280xp-qmp-ufs-phy - - qcom,sdm845-qmp-ufs-phy - - qcom,sm6115-qmp-ufs-phy - - qcom,sm6125-qmp-ufs-phy - - qcom,sm6350-qmp-ufs-phy - - qcom,sm7150-qmp-ufs-phy - - qcom,sm8150-qmp-ufs-phy - - qcom,sm8250-qmp-ufs-phy - - qcom,sm8350-qmp-ufs-phy - - qcom,sm8450-qmp-ufs-phy - - qcom,sm8475-qmp-ufs-phy - - qcom,sm8550-qmp-ufs-phy - - qcom,sm8650-qmp-ufs-phy + oneOf: + - items: + - enum: + - qcom,qcs615-qmp-ufs-phy + - const: qcom,sm6115-qmp-ufs-phy + - enum: + - qcom,msm8996-qmp-ufs-phy + - qcom,msm8998-qmp-ufs-phy + - qcom,sa8775p-qmp-ufs-phy + - qcom,sc7180-qmp-ufs-phy + - qcom,sc7280-qmp-ufs-phy + - qcom,sc8180x-qmp-ufs-phy + - qcom,sc8280xp-qmp-ufs-phy + - qcom,sdm845-qmp-ufs-phy + - qcom,sm6115-qmp-ufs-phy + - qcom,sm6125-qmp-ufs-phy + - qcom,sm6350-qmp-ufs-phy + - qcom,sm7150-qmp-ufs-phy + - qcom,sm8150-qmp-ufs-phy + - qcom,sm8250-qmp-ufs-phy + - qcom,sm8350-qmp-ufs-phy + - qcom,sm8450-qmp-ufs-phy + - qcom,sm8475-qmp-ufs-phy + - qcom,sm8550-qmp-ufs-phy + - qcom,sm8650-qmp-ufs-phy reg: maxItems: 1 -- cgit v1.2.3 From 26fb23ce35e2d2233f810069ab11210851acbf54 Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Wed, 16 Oct 2024 20:04:06 -0700 Subject: dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 QMP PCIe PHY Gen4 x8 PCIe 3rd instance of X1E80100 supports Gen 4 x8 which needs different 8 lane capable QMP PCIe PHY with hardware revision v6.30. Document Gen 4 x8 PHY as separate module. Signed-off-by: Qiang Yu Reviewed-by: Krzysztof Kozlowski Acked-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20241017030412.265000-2-quic_qianyu@quicinc.com Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml index dcf4fa55fbba..680ec3113c2b 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -41,6 +41,7 @@ properties: - qcom,x1e80100-qmp-gen3x2-pcie-phy - qcom,x1e80100-qmp-gen4x2-pcie-phy - qcom,x1e80100-qmp-gen4x4-pcie-phy + - qcom,x1e80100-qmp-gen4x8-pcie-phy reg: minItems: 1 @@ -172,6 +173,7 @@ allOf: - qcom,sc8280xp-qmp-gen3x2-pcie-phy - qcom,sc8280xp-qmp-gen3x4-pcie-phy - qcom,x1e80100-qmp-gen4x4-pcie-phy + - qcom,x1e80100-qmp-gen4x8-pcie-phy then: properties: clocks: @@ -201,6 +203,7 @@ allOf: - qcom,sm8550-qmp-gen4x2-pcie-phy - qcom,sm8650-qmp-gen4x2-pcie-phy - qcom,x1e80100-qmp-gen4x2-pcie-phy + - qcom,x1e80100-qmp-gen4x8-pcie-phy then: properties: resets: -- cgit v1.2.3 From 0217f4aef0b07a57086baeed9c0ac05160435a45 Mon Sep 17 00:00:00 2001 From: Frank Wang Date: Wed, 16 Oct 2024 15:37:12 +0800 Subject: dt-bindings: phy: rockchip,inno-usb2phy: add rk3576 Add compatible for the USB2 phy in the Rockchip RK3576 SoC. This change also refactor the clocks list as there are new clocks adding used for the USB MMU in RK3576 SoC. Signed-off-by: Frank Wang Reviewed-by: Krzysztof Kozlowski Reviewed-by: Heiko Stuebner Link: https://lore.kernel.org/r/20241016073713.14133-3-frawang.cn@gmail.com Signed-off-by: Vinod Koul --- .../bindings/phy/rockchip,inno-usb2phy.yaml | 45 +++++++++++++++++++++- 1 file changed, 43 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml index 5254413137c6..6a7ef556414c 100644 --- a/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml +++ b/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml @@ -20,6 +20,7 @@ properties: - rockchip,rk3366-usb2phy - rockchip,rk3399-usb2phy - rockchip,rk3568-usb2phy + - rockchip,rk3576-usb2phy - rockchip,rk3588-usb2phy - rockchip,rv1108-usb2phy @@ -34,10 +35,15 @@ properties: const: 0 clocks: - maxItems: 1 + minItems: 1 + maxItems: 3 clock-names: - const: phyclk + minItems: 1 + items: + - const: phyclk + - const: aclk + - const: aclk_slv assigned-clocks: description: @@ -172,6 +178,41 @@ allOf: - interrupts - interrupt-names + - if: + properties: + compatible: + contains: + enum: + - rockchip,px30-usb2phy + - rockchip,rk3128-usb2phy + - rockchip,rk3228-usb2phy + - rockchip,rk3308-usb2phy + - rockchip,rk3328-usb2phy + - rockchip,rk3366-usb2phy + - rockchip,rk3399-usb2phy + - rockchip,rk3568-usb2phy + - rockchip,rk3588-usb2phy + - rockchip,rv1108-usb2phy + then: + properties: + clocks: + maxItems: 1 + clock-names: + maxItems: 1 + + - if: + properties: + compatible: + contains: + enum: + - rockchip,rk3576-usb2phy + then: + properties: + clocks: + minItems: 3 + clock-names: + minItems: 3 + additionalProperties: false examples: -- cgit v1.2.3 From b3e804ab9aad465ba7285aa5daf83656d5efc59f Mon Sep 17 00:00:00 2001 From: Frank Wang Date: Mon, 14 Oct 2024 10:03:41 +0800 Subject: dt-bindings: phy: rockchip-usbdp: add rk3576 Add compatible for the USBDP phy in the Rockchip RK3576 SoC. Signed-off-by: Frank Wang Acked-by: Rob Herring (Arm) Reviewed-by: Heiko Stuebner Reviewed-by: Dragan Simic Link: https://lore.kernel.org/r/20241014020342.15974-1-frawang.cn@gmail.com Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml index 1f1f8863b80d..b42f1272903d 100644 --- a/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml @@ -13,6 +13,7 @@ maintainers: properties: compatible: enum: + - rockchip,rk3576-usbdp-phy - rockchip,rk3588-usbdp-phy reg: -- cgit v1.2.3 From 7adb3d221a4d6a4f5e0793c3bd35f1168934035c Mon Sep 17 00:00:00 2001 From: Soutrik Mukhopadhyay Date: Fri, 4 Oct 2024 16:00:42 +0530 Subject: dt-bindings: phy: Add eDP PHY compatible for sa8775p Add compatible string for the supported eDP PHY on sa8775p platform. Acked-by: Krzysztof Kozlowski Signed-off-by: Soutrik Mukhopadhyay Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20241004103046.22209-2-quic_mukhopad@quicinc.com Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml index 4e15d90d08b0..293fb6a9b1c3 100644 --- a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml @@ -17,6 +17,7 @@ description: properties: compatible: enum: + - qcom,sa8775p-edp-phy - qcom,sc7280-edp-phy - qcom,sc8180x-edp-phy - qcom,sc8280xp-dp-phy -- cgit v1.2.3 From 2ac03d0811b94c2397d5ec3c82a65a112aeab5b0 Mon Sep 17 00:00:00 2001 From: Macpaul Lin Date: Sat, 12 Oct 2024 11:50:16 +0800 Subject: dt-bindings: phy: mediatek: tphy: add a property for power-domains Include the MediaTek TPHY in a power domain. Add the 'power-domains' property in the Device Tree (DT) Schema and set 'maxItems: 1'. Also, include a reminder in the description of the 'power-domains' property. Signed-off-by: Macpaul Lin Reviewed-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20241012035016.17667-1-macpaul.lin@mediatek.com Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/mediatek,tphy.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml index 423b7c4e62f2..6be3aa4557e5 100644 --- a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml +++ b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml @@ -125,6 +125,16 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 default: 28 + power-domains: + description: + The TPHY of MediaTek should exist within a power domain. The + developer should be aware that the hardware design of MediaTek TPHY + does not require the addition of MTCMOS. If the power to the TPHY + is turned off, it will impact other functions. From the current + perspective of USB hardware design, even if MTCMOS is added to the + TPHY, it should remain always on. + maxItems: 1 + # Required child node: patternProperties: "^(usb|pcie|sata)-phy@[0-9a-f]+$": -- cgit v1.2.3 From de30906910f8c2a91b236ff77d7dd5edfb14bb55 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 7 Oct 2024 18:27:32 +0200 Subject: dt-bindings: phy: rk3228-hdmi-phy: convert to yaml Convert the binding to yaml and rename it according to its first compatible instead of the unspecific rockchip-inno-hdmi naming. Signed-off-by: Heiko Stuebner Reviewed-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20241007162732.2450168-1-heiko@sntech.de Signed-off-by: Vinod Koul --- .../bindings/phy/phy-rockchip-inno-hdmi.txt | 43 ---------- .../bindings/phy/rockchip,rk3228-hdmi-phy.yaml | 97 ++++++++++++++++++++++ 2 files changed, 97 insertions(+), 43 deletions(-) delete mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-inno-hdmi.txt create mode 100644 Documentation/devicetree/bindings/phy/rockchip,rk3228-hdmi-phy.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-hdmi.txt b/Documentation/devicetree/bindings/phy/phy-rockchip-inno-hdmi.txt deleted file mode 100644 index 710cccd5ee56..000000000000 --- a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-hdmi.txt +++ /dev/null @@ -1,43 +0,0 @@ -ROCKCHIP HDMI PHY WITH INNO IP BLOCK - -Required properties: - - compatible : should be one of the listed compatibles: - * "rockchip,rk3228-hdmi-phy", - * "rockchip,rk3328-hdmi-phy"; - - reg : Address and length of the hdmi phy control register set - - clocks : phandle + clock specifier for the phy clocks - - clock-names : string, clock name, must contain "sysclk" for system - control and register configuration, "refoclk" for crystal- - oscillator reference PLL clock input and "refpclk" for pclk- - based refeference PLL clock input. - - #clock-cells: should be 0. - - clock-output-names : shall be the name for the output clock. - - interrupts : phandle + interrupt specified for the hdmiphy interrupt - - #phy-cells : must be 0. See ./phy-bindings.txt for details. - -Optional properties for rk3328-hdmi-phy: - - nvmem-cells = phandle + nvmem specifier for the cpu-version efuse - - nvmem-cell-names : "cpu-version" to read the chip version, required - for adjustment to some frequency settings - -Example: - hdmi_phy: hdmi-phy@12030000 { - compatible = "rockchip,rk3228-hdmi-phy"; - reg = <0x12030000 0x10000>; - #phy-cells = <0>; - clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>, <&cru DCLK_HDMIPHY>; - clock-names = "sysclk", "refoclk", "refpclk"; - #clock-cells = <0>; - clock-output-names = "hdmi_phy"; - status = "disabled"; - }; - -Then the PHY can be used in other nodes such as: - - hdmi: hdmi@200a0000 { - compatible = "rockchip,rk3228-dw-hdmi"; - ... - phys = <&hdmi_phy>; - phy-names = "hdmi"; - ... - }; diff --git a/Documentation/devicetree/bindings/phy/rockchip,rk3228-hdmi-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,rk3228-hdmi-phy.yaml new file mode 100644 index 000000000000..ac15bf857ef9 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/rockchip,rk3228-hdmi-phy.yaml @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/rockchip,rk3228-hdmi-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip HDMI PHY with Innosilicon IP block + +maintainers: + - Heiko Stuebner + +properties: + compatible: + enum: + - rockchip,rk3228-hdmi-phy + - rockchip,rk3328-hdmi-phy + + reg: + maxItems: 1 + + clocks: + maxItems: 3 + + clock-names: + items: + - const: sysclk + - const: refoclk + - const: refpclk + + clock-output-names: + description: + The hdmiphy output clock name, that gets fed back to the CRU. + + "#clock-cells": + const: 0 + + interrupts: + maxItems: 1 + + nvmem-cells: + maxItems: 1 + description: A phandle + nvmem specifier for the cpu-version efuse + for adjustment to some frequency settings, depending on cpu-version + + nvmem-cell-names: + items: + - const: cpu-version + + '#phy-cells': + const: 0 + +required: + - compatible + - reg + - clocks + - clock-names + - clock-output-names + - '#clock-cells' + - '#phy-cells' + +allOf: + - if: + properties: + compatible: + contains: + const: rockchip,rk3228-hdmi-phy + + then: + properties: + interrupts: false + + - if: + properties: + compatible: + contains: + const: rockchip,rk3328-hdmi-phy + + then: + required: + - interrupts + +additionalProperties: false + +examples: + - | + + #include + hdmi_phy: phy@12030000 { + compatible = "rockchip,rk3228-hdmi-phy"; + reg = <0x12030000 0x10000>; + #phy-cells = <0>; + clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>, <&cru DCLK_HDMI_PHY>; + clock-names = "sysclk", "refoclk", "refpclk"; + #clock-cells = <0>; + + clock-output-names = "hdmi_phy"; + }; -- cgit v1.2.3 From 76b4f2a5cec59e842de4b5989eb990a2ee8cedf3 Mon Sep 17 00:00:00 2001 From: Xu Yang Date: Thu, 26 Sep 2024 15:39:47 +0800 Subject: dt-bindings: phy: mxs-usb-phy: add imx8qxp compatible Add "fsl,imx8qxp-usbphy" compatible. Signed-off-by: Xu Yang Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20240926073951.783869-2-xu.yang_2@nxp.com Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/fsl,mxs-usbphy.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/fsl,mxs-usbphy.yaml b/Documentation/devicetree/bindings/phy/fsl,mxs-usbphy.yaml index ce665a2779b7..d01b7d187040 100644 --- a/Documentation/devicetree/bindings/phy/fsl,mxs-usbphy.yaml +++ b/Documentation/devicetree/bindings/phy/fsl,mxs-usbphy.yaml @@ -32,6 +32,7 @@ properties: - enum: - fsl,imx8dxl-usbphy - fsl,imx8qm-usbphy + - fsl,imx8qxp-usbphy - fsl,imx8ulp-usbphy - const: fsl,imx7ulp-usbphy -- cgit v1.2.3 From 2df490e7374de8e940d353cfcafd3c91242841ea Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 30 Aug 2024 11:20:45 +0300 Subject: dt-bindings: phy: add NXP PTN3222 eUSB2 to USB2 redriver The NXP PTN3222 is the single-port eUSB2 to USB2 redriver that performs translation between eUSB2 and USB2 signalling schemes. It supports all three data rates: Low Speed, Full Speed and High Speed. Reviewed-by: Conor Dooley Signed-off-by: Dmitry Baryshkov Reviewed-by: Stephan Gerhold Link: https://lore.kernel.org/r/20240830-nxp-ptn3222-v2-1-4c6d8535cf6c@linaro.org Signed-off-by: Vinod Koul --- .../devicetree/bindings/phy/nxp,ptn3222.yaml | 55 ++++++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/nxp,ptn3222.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/nxp,ptn3222.yaml b/Documentation/devicetree/bindings/phy/nxp,ptn3222.yaml new file mode 100644 index 000000000000..acec5bb2391d --- /dev/null +++ b/Documentation/devicetree/bindings/phy/nxp,ptn3222.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/nxp,ptn3222.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP PTN3222 1-port eUSB2 to USB2 redriver + +maintainers: + - Dmitry Baryshkov + +properties: + compatible: + enum: + - nxp,ptn3222 + + reg: + maxItems: 1 + + "#phy-cells": + const: 0 + + vdd1v8-supply: + description: power supply (1.8V) + + vdd3v3-supply: + description: power supply (3.3V) + + reset-gpios: true + +required: + - compatible + - reg + - '#phy-cells' + +additionalProperties: false + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + redriver@4f { + compatible = "nxp,ptn3222"; + reg = <0x4f>; + #phy-cells = <0>; + vdd3v3-supply = <&vreg_3p3>; + vdd1v8-supply = <&vreg_1p8>; + reset-gpios = <&gpio_reset GPIO_ACTIVE_LOW>; + }; + }; +... -- cgit v1.2.3 From 26ac85e3adb4775df42d94b310276b06c0898d3d Mon Sep 17 00:00:00 2001 From: Ilya Orazov Date: Sun, 15 Sep 2024 17:18:31 +0300 Subject: dt-bindings: phy: ti,tcan104x-can: Document Microchip ATA6561 Microchip ATA6561 is High-Speed CAN Transceiver with Standby Mode. It is pin-compatible with TI TCAN1042 and has a compatible programming model, therefore use ti,tcan1042 as fallback compatible. Acked-by: Conor Dooley Signed-off-by: Ilya Orazov Link: https://lore.kernel.org/r/20240915141831.2809208-2-ilordash02@gmail.com Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/ti,tcan104x-can.yaml | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/ti,tcan104x-can.yaml b/Documentation/devicetree/bindings/phy/ti,tcan104x-can.yaml index 79dad3e89aa6..4a8c3829d85d 100644 --- a/Documentation/devicetree/bindings/phy/ti,tcan104x-can.yaml +++ b/Documentation/devicetree/bindings/phy/ti,tcan104x-can.yaml @@ -14,10 +14,15 @@ properties: pattern: "^can-phy" compatible: - enum: - - nxp,tjr1443 - - ti,tcan1042 - - ti,tcan1043 + oneOf: + - items: + - enum: + - microchip,ata6561 + - const: ti,tcan1042 + - enum: + - ti,tcan1042 + - ti,tcan1043 + - nxp,tjr1443 '#phy-cells': const: 0 -- cgit v1.2.3 From 8e1e94619bd37915323a199ceed39ed5904e7fa6 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 17 Oct 2024 20:42:56 +0300 Subject: dt-bindings: phy: qcom: snps-eusb2: Add SAR2130P compatible Document the Synopsys eUSB2 PHY on the SAR2130P platform by using the SM8550 as fallback. Signed-off-by: Dmitry Baryshkov Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20241017-sar2130p-eusb2-v1-1-1cedd674ec64@linaro.org Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/qcom,snps-eusb2-phy.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/qcom,snps-eusb2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,snps-eusb2-phy.yaml index b82f7f5731ed..142b3c8839d6 100644 --- a/Documentation/devicetree/bindings/phy/qcom,snps-eusb2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,snps-eusb2-phy.yaml @@ -17,6 +17,7 @@ properties: oneOf: - items: - enum: + - qcom,sar2130p-snps-eusb2-phy - qcom,sdx75-snps-eusb2-phy - qcom,sm8650-snps-eusb2-phy - qcom,x1e80100-snps-eusb2-phy -- cgit v1.2.3 From 30c280bc8e4555d55d7de7b85983990356c1e8e9 Mon Sep 17 00:00:00 2001 From: Xin Liu Date: Fri, 18 Oct 2024 13:57:50 +0800 Subject: dt-bindings: phy: Add QMP UFS PHY compatible for QCS8300 Document the QMP UFS PHY compatible for Qualcomm QCS8300 to support physical layer functionality for UFS found on the SoC. Use fallback to indicate the compatibility of the QMP UFS PHY on the QCS8300 with that on the SA8775P. Signed-off-by: Xin Liu Reviewed-by: Krzysztof Kozlowski Signed-off-by: Jingyi Wang Link: https://lore.kernel.org/r/20241018-qcs8300_ufs_phy_binding-v4-1-261c7c5fb8ff@quicinc.com Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml index a93d64d1c55b..72bed2933b03 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml @@ -20,6 +20,10 @@ properties: - enum: - qcom,qcs615-qmp-ufs-phy - const: qcom,sm6115-qmp-ufs-phy + - items: + - enum: + - qcom,qcs8300-qmp-ufs-phy + - const: qcom,sa8775p-qmp-ufs-phy - enum: - qcom,msm8996-qmp-ufs-phy - qcom,msm8998-qmp-ufs-phy -- cgit v1.2.3 From c3639d423d76c935b58827296a124e8f13d79b4b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Fri, 13 Sep 2024 06:45:56 +0200 Subject: dt-bindings: phy: bcm-ns-usb2-phy: drop deprecated variant MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The old binding variant (the one covering whole DMU block) was deprecated 3 years ago. Linux kernel was warning when using it for similar amount of time. There aren't any known Northstar devices with bootloader providing DT to operating system. Actually OpenWrt seems to be the only project using this binding and it always appends DTB to kernel. It has switched to the non-deprecated binding years ago. Given there is close to zero chance this breaks anyone's setup it should more than safe to drop this binding variant after 3 years. Signed-off-by: Rafał Miłecki Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20240913044557.28315-1-zajec5@gmail.com Signed-off-by: Vinod Koul --- .../devicetree/bindings/phy/bcm-ns-usb2-phy.yaml | 19 +++---------------- 1 file changed, 3 insertions(+), 16 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/bcm-ns-usb2-phy.yaml b/Documentation/devicetree/bindings/phy/bcm-ns-usb2-phy.yaml index 426101530a21..d72c02ab55ae 100644 --- a/Documentation/devicetree/bindings/phy/bcm-ns-usb2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/bcm-ns-usb2-phy.yaml @@ -18,16 +18,8 @@ properties: const: brcm,ns-usb2-phy reg: - anyOf: - - maxItems: 1 - description: PHY control register - - maxItems: 1 - description: iomem address range of DMU (Device Management Unit) - deprecated: true - - reg-names: - items: - - const: dmu + maxItems: 1 + description: PHY control register brcm,syscon-clkset: description: phandle to syscon for clkset register @@ -50,12 +42,7 @@ required: - clocks - clock-names - "#phy-cells" - -oneOf: - - required: - - brcm,syscon-clkset - - required: - - reg-names + - brcm,syscon-clkset additionalProperties: false -- cgit v1.2.3 From c5699055472ead216c38236476c62bf43fcc3ca3 Mon Sep 17 00:00:00 2001 From: Daniel Machon Date: Mon, 9 Sep 2024 17:14:48 +0200 Subject: dt-bindings: phy: sparx5: document lan969x Lan969x is going to reuse the existing Sparx5 SERDES driver - document that by adding compatible strings for the different SKU's that we support, and a short description of the SERDES types and data rates supported. Signed-off-by: Daniel Machon Reviewed-by: Steen Hegelund Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240909-sparx5-lan969x-serdes-driver-v2-8-d695bcb57b84@microchip.com Signed-off-by: Vinod Koul --- .../bindings/phy/microchip,sparx5-serdes.yaml | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/phy/microchip,sparx5-serdes.yaml b/Documentation/devicetree/bindings/phy/microchip,sparx5-serdes.yaml index bdbdb3bbddbe..fa0b02916dac 100644 --- a/Documentation/devicetree/bindings/phy/microchip,sparx5-serdes.yaml +++ b/Documentation/devicetree/bindings/phy/microchip,sparx5-serdes.yaml @@ -8,6 +8,7 @@ title: Microchip Sparx5 Serdes controller maintainers: - Steen Hegelund + - Daniel Machon description: | The Sparx5 SERDES interfaces share the same basic functionality, but @@ -62,12 +63,26 @@ description: | * 10.3125 Gbps (10GBASE-R/10GBASE-KR/USXGMII) * 25.78125 Gbps (25GBASE-KR/25GBASE-CR/25GBASE-SR/25GBASE-LR/25GBASE-ER) + lan969x has ten SERDES10G interfaces that share the same features, operating + modes and data rates as the equivalent Sparx5 SERDES10G interfaces. + properties: $nodename: pattern: "^serdes@[0-9a-f]+$" compatible: - const: microchip,sparx5-serdes + oneOf: + - enum: + - microchip,sparx5-serdes + - microchip,lan9691-serdes + - items: + - enum: + - microchip,lan9698-serdes + - microchip,lan9696-serdes + - microchip,lan9694-serdes + - microchip,lan9693-serdes + - microchip,lan9692-serdes + - const: microchip,lan9691-serdes reg: minItems: 1 -- cgit v1.2.3