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2020-01-27Merge branch 'for-5.6/logitech' into for-linusJiri Kosina
- voltage support for newer Logitech HID++ devices, from Pedro Vanzella. - MX Master support improvements, from Adrian Freund and Mazin Rezk
2020-01-27Merge branch 'for-5.6/hidraw' into for-linusJiri Kosina
- support for uniq ioctl()
2020-01-27thermal: stm32: Fix low threshold interrupt floodPascal Paillet
With the STM32 thermal peripheral, it is not possible to dump the temperature that has caused the interrupt. When the temperature reaches the low threshold, we generally read a temperature that is a little bit higher than the low threshold. This maybe due to sampling precision, and also because the CPU becomes hotter when it quits WFI mode. In that case, the framework does not change the trip points. This leads to a lot of low threshold interrupts. The fix is to set the low threshold value 0.5 degrees Celsius below the actual request. The problem is not so frequent with the high threshold and it would no be a good idea to set the threshold value higher than the request. Signed-off-by: Pascal Paillet <p.paillet@st.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20200110101605.24984-7-p.paillet@st.com
2020-01-27thermal: stm32: Improve temperature computingPascal Paillet
Change the way of computing to avoid rounds by 1 or 2 degrees. Also simplify the sampling time management that is hard-coded to maximum value during probe. Signed-off-by: Pascal Paillet <p.paillet@st.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20200110101605.24984-6-p.paillet@st.com
2020-01-27thermal: stm32: Handle multiple trip pointsPascal Paillet
Let the thermal framework handle the trip points instead of custom code inside the driver. This is backward compatible, simplifies the driver and offers the possibility to the user to set any trip point he needs. stm_thermal_set_trips callback that is registered to set_trips ops to handle the low and high thresholds and replaces stm_thermal_set_threshold and stm_thermal_update_threshold functions. modify irq enable to handle the thresholds. Signed-off-by: Pascal Paillet <p.paillet@st.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20200110101605.24984-5-p.paillet@st.com
2020-01-27thermal: stm32: Disable interrupts at probePascal Paillet
In case of CPU reset, the interrupts could be enabled at boot time. Disable interrupts and clear flags. Signed-off-by: Pascal Paillet <p.paillet@st.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20200110101605.24984-4-p.paillet@st.com
2020-01-27thermal: stm32: Rework sensor mode managementPascal Paillet
Be sure get_temp returns an error while disabling or enabling the device. Set THERMAL_DEVICE_ENABLED state at the end of power on function. Set THERMAL_DEVICE_DISABLED state at the beginning of power off function. Signed-off-by: Pascal Paillet <p.paillet@st.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20200110101605.24984-3-p.paillet@st.com
2020-01-27thermal: stm32: Fix icifr register namePascal Paillet
Fix a mistake with the ICIFR register name. Signed-off-by: Pascal Paillet <p.paillet@st.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20200110101605.24984-2-p.paillet@st.com
2020-01-27thermal: of: Make thermal_zone_of_sensor_register return -ENODEV if a sensor ↵Peter Mamonov
OF node is missing When devm_thermal_zone_of_sensor_register() is called from hwmon_thermal_add_sensor() it is possible that the relevant sensor is missing an OF node. In this case thermal_zone_of_sensor_register() returns -EINVAL which causes hwmon_thermal_add_sensor() to fail as well. This patch changes relevant return code of thermal_zone_of_sensor_register() to -ENODEV, which is tolerated by hwmon_thermal_add_sensor(). Here is a particular case of such behaviour: the Marvell ethernet PHYs driver registers hwmon device for the built-in temperature sensor (see drivers/net/phy/marvell.c). Since the sensor doesn't have associated OF node devm_hwmon_device_register() returns error which ultimately causes failure of the PHY driver's probe function. Signed-off-by: Peter Mamonov <pmamonov@gmail.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20190827143952.19591-1-pmamonov@gmail.com
2020-01-27qed: FW 8.42.2.0 debug featuresMichal Kalderon
Add to debug dump more information on the platform it was collected from (pci func, path id). Provide human readable reg fifo erros. Removed static debug arrays from HSI Functions, and move them to the hwfn. Some structures were slightly changed (removing reserved chip id for example) which lead to many long initializations being modified with one parameter less during initialization. This leads to some long diffs that don't really change anything. Signed-off-by: Ariel Elior <ariel.elior@marvell.com> Signed-off-by: Michal Kalderon <michal.kalderon@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-01-27qed: rt init valid initialization changedMichal Kalderon
The QM phase init tool can be invoked multiple times during the driver lifetime. Part of the init comes from the runtime array. The logic for setting the values did not init all values, basically assuming the runtime array was all zeroes. But if it was invoked multiple times, nobody was zeroing it after the first time. In this change we zero the runtime array right after using it. Signed-off-by: Ariel Elior <ariel.elior@marvell.com> Signed-off-by: Michal Kalderon <michal.kalderon@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-01-27qed: Debug feature: ilt and mdumpMichal Kalderon
Part of the FW drop includes new debug capabilities implemented in the qed_debug file. This patch dumps additional information during ethtool -d for better debugging. The data dumped is the ilt (internal logical table) and information gathered by the management firmware incase there was a crash and driver was not able to extract the information (mdump). Signed-off-by: Ariel Elior <ariel.elior@marvell.com> Signed-off-by: Michal Kalderon <michal.kalderon@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-01-27qed: FW 8.42.2.0 Add fw overlay featureMichal Kalderon
This feature enables the FW to page out FW code when required Signed-off-by: Ariel Elior <ariel.elior@marvell.com> Signed-off-by: Michal Kalderon <michal.kalderon@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-01-27qed: FW 8.42.2.0 HSI changesMichal Kalderon
This patch contains several HSI changes. The changes are part of features like RDMA VF and OVS, the patch also contains a fix to how the init code determines if the dmae is ready to be used. Signed-off-by: Ariel Elior <ariel.elior@marvell.com> Signed-off-by: Michal Kalderon <michal.kalderon@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-01-27qed: FW 8.42.2.0 iscsi/fcoe changesMichal Kalderon
- Remove struct iscsi_slow_path_hdr and field fw_cid from several structs - Remove struct iscsi_spe_func_dstry - Remove fields pbe_page_size_log and pbl_page_size_log from struct iscsi_conn_offload_param Signed-off-by: Manish Rangankar <manish.rangankar@marvell.com> Signed-off-by: Saurav Kashyap <saurav.kashyap@marvell.com> Signed-off-by: Ariel Elior <ariel.elior@marvell.com> Signed-off-by: Michal Kalderon <michal.kalderon@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-01-27qed: Add abstraction for different hsi values per chipMichal Kalderon
The number of BTB blocks was modified to be different between the two chip flavors supported (BB/K2) as a result, this lead to a re-write of selecting the default hsi value based on the chip. This patch creates a lookup table for hsi values per chip rather than ask again and again for every value. Signed-off-by: Ariel Elior <ariel.elior@marvell.com> Signed-off-by: Michal Kalderon <michal.kalderon@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-01-27qed: FW 8.42.2.0 Additional ll2 typeMichal Kalderon
LL2 queues were a limited resource due to FW constraints. This FW introduced a new resource which is a context based ll2 queue (memory on host). The additional ll2 queues are required for RDMA SRIOV. The code refers to the previous ll2 queues as ram-based or legacy, and the new queues as ctx-based. This change decreased the "legacy" ram-based queues therefore the first ll2 queue used for iWARP was converted to the ctx-based ll2 queue. This feature also exposed a bug in the DIRECT_REG_WR64 macro implementation which didn't have an effect in other use cases. Signed-off-by: Ariel Elior <ariel.elior@marvell.com> Signed-off-by: Michal Kalderon <michal.kalderon@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-01-27qed: Use dmae to write to widebus registers in fw_funcsMichal Kalderon
There are several wide-bus registers written to by the fw_funcs that require using the dmae for atomicity. Therefore using the dmae channel functionality was added to the fw_funcs file, since the code is very similar to the previously used code, the structures used were moved to qed_hsi. Due to FW conventions, the names of the flags in the struct changed. Since this required slight modification in the places that set the flags the code was modified to use GET/SET FIELD macros. Signed-off-by: Ariel Elior <ariel.elior@marvell.com> Signed-off-by: Michal Kalderon <michal.kalderon@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-01-27qed: FW 8.42.2.0 Parser offsets modifiedMichal Kalderon
Convert storm ram line to regpair rather than two distinct u32 to better represent the u64 width of the ram. Convert some defines to be hex instead of negative values these values also changed by FW from previous value. Signed-off-by: Ariel Elior <ariel.elior@marvell.com> Signed-off-by: Michal Kalderon <michal.kalderon@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-01-27qed: FW 8.42.2.0 Queue Manager changesMichal Kalderon
This patch contains changes in initialization and usage of the QM blocks. Instead of setting a rate limiter per vport the rate limiters are now a global resource and set independentaly. The patch also contains a field name change: vport_wfq which is part of vport_params was renamed to wfq as the vport prefix is redundant. Signed-off-by: Ariel Elior <ariel.elior@marvell.com> Signed-off-by: Michal Kalderon <michal.kalderon@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-01-27qed: FW 8.42.2.0 Expose new registers and change windowsMichal Kalderon
This patch contains register initialization related changes. - Modifications to the runtime offsets - these are defines used by the driver or firmware functions to set values that are used by the initialization functions to set device register values. - Global window values changes to provide different device register ranges. - Additional device registers addresses were added to the register file, used in later stages. Signed-off-by: Ariel Elior <ariel.elior@marvell.com> Signed-off-by: Michal Kalderon <michal.kalderon@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-01-27qed: FW 8.42.2.0 Internal ram offsets modificationsMichal Kalderon
IRO stands for internal RAM offsets. Updating the FW binary produces different iro offsets. This file contains the different values, and a new representation of the values. Update the FW version Signed-off-by: Ariel Elior <ariel.elior@marvell.com> Signed-off-by: Michal Kalderon <michal.kalderon@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-01-27octeontx2-pf: ethtool RSS config supportSunil Goutham
Added support to show or configure RSS hash key, indirection table, 2,4 tuple via ethtool. Also added debug msg_level support to dump messages when HW reports errors in packet received or transmitted. Signed-off-by: Prakash Brahmajyosyula <bprakash@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-01-27octeontx2-pf: Add basic ethtool supportChristina Jacob
This patch adds ethtool support for - Driver stats, Tx/Rx perqueue and CGX LMAC stats - Set/show Rx/Tx queue count - Set/show Rx/Tx ring sizes - Set/show IRQ coalescing parameters Signed-off-by: Christina Jacob <cjacob@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-01-27octeontx2-pf: Add ndo_get_stats64Geetha sowjanya
Added ndo_get_stats64 which returns stats maintained by HW. Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-01-27octeontx2-pf: TCP segmentation offload supportSunil Goutham
Adds TCP segmentation offload (TSO) support. First version of the silicon didn't support TSO offload, for this driver level TSO support is added. Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-01-27octeontx2-pf: Receive side scaling supportSunil Goutham
Adds receive side scaling (RSS) support to distribute pkts/flows across multiple queues. Sets up key, indirection table etc. Also added extraction of HW calculated rxhash and adding to same to SKB ie NETIF_F_RXHASH offload support. Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-01-27octeontx2-pf: Error handling supportGeetha sowjanya
HW reports many errors on the receive and transmit paths. Such as incorrect queue configuration, pkt transmission errors, LMTST instruction errors, transmit queue full etc. These are reported via QINT interrupt. Most of the errors are fatal and needs reinitialization. Also added support to allocate receive buffers in non-atomic context when allocation fails in NAPI context. Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Aleksey Makarov <amakarov@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-01-27octeontx2-pf: MTU, MAC and RX mode config supportSunil Goutham
This patch addes support to change interface MTU, MAC address retrieval and config, RX mode ie unicast, multicast and promiscuous. Also added link loopback support Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com> Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-01-27octeontx2-pf: Register and handle link notificationsLinu Cherian
PF and AF (admin function) shares 64KB of reserved memory region for communication. This region is shared for - Messages sent by PF and responses sent by AF. - Notifications sent by AF and ACKs sent by PF. This patch adds infrastructure to handle notifications sent by AF and adds handlers to process them. One of the main usecase of notifications from AF is physical link changes. So this patch adds registration of PF with AF to receive link status change notifications and also adds the handler for that notification. Signed-off-by: Linu Cherian <lcherian@marvell.com> Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-01-27octeontx2-pf: Add packet transmission supportSunil Goutham
This patch adds the packet transmission support. For a given skb prepares send queue descriptors (SQEs) and pushes them to HW. Here driver doesn't maintain it's own SQ rings, SQEs are pushed to HW using a silicon specific operations called LMTST. From the instuction HW derives the transmit queue number and queues the SQE to that queue. These LMTST instructions are designed to avoid queue maintenance in SW and lockless behavior ie when multiple cores are trying to add SQEs to same queue then HW will takecare of serialization, no need for SW to hold locks. Also supports scatter/gather. Co-developed-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-01-27octeontx2-pf: Receive packet handling supportSunil Goutham
Added receive packet handling (NAPI) support, error stats, RX_ALL capability config option to passon error pkts to stack upon user request. In subsequent patches these error stats will be added to ethttool. Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-01-27octeontx2-pf: Setup interrupts and NAPI handlerSunil Goutham
Completion queue (CQ) is the one with which HW notifies SW on a packet reception or transmission. Each of the RQ and SQ are mapped to a unique CQ and again both CQs are mapped to same interrupt ie the CINT. So that each core has one interrupt source in whose handler both Rx and Tx notifications are processed. Also - Registered a NAPI handler for the CINT. - Setup coalescing parameters. - IRQ affinity hints etc Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-01-27octeontx2-pf: Initialize and config queuesSunil Goutham
This patch does the initialization of all queues ie the receive buffer pools, receive and transmit queues, completion or notification queues etc. Allocates all required resources (eg transmit schedulers, receive buffers etc) and configures them for proper functioning of queues. Also sets up receive queue's RED dropping levels. Co-developed-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-01-27octeontx2-pf: Attach NIX and NPA block LFsSunil Goutham
For a PF to function as a NIC, NPA (for Rx buffers, Tx descriptors etc) and NIX (for rcv, send and completion queues) are the minimum resources needed. So request admin function (AF) to attach one each of NIX and NPA block LFs (local functions). Only AF can configure a LF's contexts, so request AF to allocate memory for NPA aura/pool and NIX RQ/SQ/CQ HW contexts. Upon receiving response, save some of the HW constants like number of pointers per stack page, size of send queue buffer (SQBs, where SQEs are queued by HW) e.t.c which are later used to initialize queues. A HW context here is like a state machine maintained for a descriptor queue. eg size, head/tail pointers, irq etc etc. HW maintains this in memory. Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-01-27octeontx2-pf: Mailbox communication with AFSunil Goutham
In the resource virtualization unit (RVU) each of the PF and AF (admin function) share a 64KB of reserved memory region for communication. This patch initializes PF <=> AF mailbox IRQs, registers handlers for processing these communication messages. Also adds support to process these messages in both directions ie responses to PF initiated DOWN (PF => AF) messages and AF initiated UP messages (AF => PF). Mbox communication APIs and message formats are defined in AF driver (drivers/net/ethernet/marvell/octeontx2/af), mbox.h from AF driver is included here to avoid duplication. Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Christina Jacob <cjacob@marvell.com> Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Signed-off-by: Aleksey Makarov <amakarov@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-01-27octeontx2-pf: Add Marvell OcteonTX2 NIC driverSunil Goutham
This patch adds template for the Marvell's OcteonTX2 network controller's physical function driver. Just the probe, PCI specific initialization and netdev registration. Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-01-27Merge git://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf-nextDavid S. Miller
Daniel Borkmann says: ==================== pull-request: bpf-next 2020-01-27 The following pull-request contains BPF updates for your *net-next* tree. We've added 20 non-merge commits during the last 5 day(s) which contain a total of 24 files changed, 433 insertions(+), 104 deletions(-). The main changes are: 1) Make BPF trampolines and dispatcher aware for the stack unwinder, from Jiri Olsa. 2) Improve handling of failed CO-RE relocations in libbpf, from Andrii Nakryiko. 3) Several fixes to BPF sockmap and reuseport selftests, from Lorenz Bauer. 4) Various cleanups in BPF devmap's XDP flush code, from John Fastabend. 5) Fix BPF flow dissector when used with port ranges, from Yoshiki Komachi. 6) Fix bpffs' map_seq_next callback to always inc position index, from Vasily Averin. 7) Allow overriding LLVM tooling for runqslower utility, from Andrey Ignatov. 8) Silence false-positive lockdep splats in devmap hash lookup, from Amol Grover. 9) Fix fentry/fexit selftests to initialize a variable before use, from John Sperbeck. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
2020-01-27sfc: move mcdi filtering codeAlex Maftei (amaftei)
Signed-off-by: Alexandru-Mihai Maftei <amaftei@solarflare.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-01-27sfc: create header for mcdi filtering codeAlex Maftei (amaftei)
Moved structs, enums, and added function prototypes. The affected functions are no longer static. Signed-off-by: Alexandru-Mihai Maftei <amaftei@solarflare.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-01-27sfc: rename mcdi filtering functions/structsAlex Maftei (amaftei)
Minor style fixes included due to name lengths changing. Signed-off-by: Alexandru-Mihai Maftei <amaftei@solarflare.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-01-27thermal: rcar_gen3_thermal: Remove temperature boundNiklas Söderlund
The hardware manual states that the operation of the sensor is not guaranteed with temperatures above 125°C, not that the readings are invalid. Remove the bound check and try to deliver temperature readings even if we are outside the guaranteed operation range. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20200117160554.3812787-3-niklas.soderlund+renesas@ragnatech.se
2020-01-27thermal: rcar_thermal: Remove temperature boundNiklas Söderlund
The hardware manual states that the operation of the sensor is not guaranteed outside the range of -45°C to 125°C, not that the readings are invalid. Remove the bound check and try to deliver temperature readings even if we are outside the guaranteed operation range. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20200117160554.3812787-2-niklas.soderlund+renesas@ragnatech.se
2020-01-27thermal: intel: intel_pch_thermal: Add Comet Lake (CML) platform supportGayatri Kammela
Add Comet Lake to the list of the platforms to support intel_pch_thermal driver. Cc: Zhang rui <rui.zhang@intel.com> Cc: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by: Gayatri Kammela <gayatri.kammela@intel.com> Acked-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20191211200043.4985-1-gayatri.kammela@intel.com
2020-01-27thermal: intel: Fix unmatched pci_release_regionChuhong Yuan
The driver calls pci_request_regions() in probe and uses pci_release_regions() in probe failure. However, it calls pci_release_region() in remove, which does match the other two calls. Use pci_release_regions() instead to unify them. Signed-off-by: Chuhong Yuan <hslester96@gmail.com> Acked-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20191206075531.18637-1-hslester96@gmail.com
2020-01-27thermal: int340x: processor_thermal: Add Jasper Lake supportSwaminathan, Nivedita
Added new PCI id for Jasper Lake processor thermal device. Signed-off-by: Swaminathan, Nivedita <nivedita.swaminathan@intel.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Acked-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20191212203025.36310-1-srinivas.pandruvada@linux.intel.com
2020-01-27thermal: brcmstb_thermal: Register different ops per processFlorian Fainelli
Since we do not have interrupts on BCM7216, we cannot have trip point crossing, the thermal subsystem expects us to provide a NULL set_trips operation in that case, so make it possible to provide per-process thermal_zone_of_device_ops Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20200114190607.29339-7-f.fainelli@gmail.com
2020-01-27thermal: brcmstb_thermal: Restructure interrupt registrationFlorian Fainelli
If we are successful grabbing the interrupt resource, then register an interrupt handler, this makes it easier to support the interrupt as being optional, which is it for 7216. Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20200114190607.29339-6-f.fainelli@gmail.com
2020-01-27thermal: brcmstb_thermal: Add 16nm process thermal parametersFlorian Fainelli
Match the 7216 compatible string in order to derive the correct 16nm process thermal parameters to obtain correct readings. Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20200114190607.29339-5-f.fainelli@gmail.com
2020-01-27thermal: brcmstb_thermal: Prepare to support a different processFlorian Fainelli
The driver is currently assuming that it is operating with a 28nm process chip, which has a specific formula to convert temperature to a code and vice versa. Update the code to support providing two key values: offset and multiplier to derive the correct formulas. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20200114190607.29339-3-f.fainelli@gmail.com
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