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path: root/drivers/clk
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2017-07-21clk: Convert to using %pOF instead of full_nameRob Herring
Now that we have a custom printf format specifier, convert users of full_name to use %pOF instead. This is preparation to remove storing of the full path string for each node. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Russell King <linux@armlinux.org.uk> Cc: Matthias Brugger <matthias.bgg@gmail.com> Cc: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Chen-Yu Tsai <wens@csie.org> Cc: "Emilio López" <emilio@elopez.com.ar> Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com> Cc: Tero Kristo <t-kristo@ti.com> Cc: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-mediatek@lists.infradead.org Cc: linux-renesas-soc@vger.kernel.org Cc: linux-tegra@vger.kernel.org Cc: linux-omap@vger.kernel.org Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: James Liao <jamesjj.liao@mediatek.com> Acked-by: Alexandre TORGUE <alexandre.torgue@st.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-21clk: qoriq: add pll clock to clock lookup tableYuantian Tang
Register each PLL and its division clocks to clock lookup table to facilitate the clock look up for clock consumer. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-21clk: qoriq: add clock configuration for ls1088a socYuantian Tang
Clock on ls1088a chip takes primary clocking input from the external SYSCLK signal. The SYSCLK input (frequency) is multiplied using multiple phase locked loops (PLL) to create a variety of frequencies which can then be passed to a variety of internal logic, including cores and peripheral IP modules. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-18Merge branch 'clk-fixes' into clk-nextStephen Boyd
* clk-fixes: clk: x86: Do not gate clocks enabled by the firmware clk: gemini: Fix reset regression
2017-07-18clk: x86: Do not gate clocks enabled by the firmwareCarlo Caione
Read the enable register to determine if the clock is already in use by the firmware. In this case avoid gating the clock. Tested-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Darren Hart (VMware) <dvhart@infradead.org> Signed-off-by: Carlo Caione <carlo@endlessm.com> Fixes: 282a4e4ce5f9 ("platform/x86: Enable Atom PMC platform clocks") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-17clk: mmp: Drop unnecessary staticJulia Lawall
Drop static on a local variable, when the variable is initialized before any possible use. Thus, the static has no benefit. The semantic patch that fixes this problem is as follows: (http://coccinelle.lip6.fr/) // <smpl> @bad exists@ position p; identifier x; type T; @@ static T x@p; ... x = <+...x...+> @@ identifier x; expression e; type T; position p != bad.p; @@ -static T x@p; ... when != x when strict ?x = e; // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-17clk: moxart: remove unnecessary staticsGustavo A. R. Silva
Remove unnecessary static on local variable _base_ in both functions moxart_of_pll_clk_init() and moxart_of_apb_clk_init(). Such variables are initialized before being used, on every execution path throughout the mentioned functions. The statics have no benefit and, removing them reduce the code size. This issue was detected using Coccinelle and the following semantic patch: @bad exists@ position p; identifier x; type T; @@ static T x@p; ... x = <+...x...+> @@ identifier x; expression e; type T; position p != bad.p; @@ -static T x@p; ... when != x when strict ?x = e; In the following log you can see the difference in the code size. Also, notice that the bss segment is reduced down to zero. This log is the output of the size command, before and after the code change: before: text data bss dec hex filename 1724 384 128 2236 8bc drivers/clk/clk-moxart.o after: text data bss dec hex filename 1697 240 0 1937 791 drivers/clk/clk-moxart.o Signed-off-by: Gustavo A. R. Silva <garsilva@embeddedor.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-17clk: qcom: clk-smd-rpm: Fix the reported rate of branchesGeorgi Djakov
As there is no way to actually query the hardware for the current clock rate, now racalc_rate() just returns the last rate that was previously set. But if the rate was not set yet, we return the bogus rate of 1000Hz. The branch clocks have the same rate as their parent, so in this case we just need to remove recalc_rate ops and then the core framework will handle this automagically. The round_rate() is unused, so remove it as well. Reported-by: Archit Taneja <architt@codeaurora.org> Fixes: 00f64b58874e ("clk: qcom: Add support for SMD-RPM Clocks") Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-17clk: mediatek: fixed static checker warning in clk_cpumux_get_parent callSean Wang
Fixed the signedness bug returning '(-22)' on the return type as u8 with removing the sanity checker in clk_cpumux_get_parent() since clk_cpumux_set_parent() always ensures validity in clk_cpumux_get_parent() got called. Fixes: 1e17de9049da ("clk: mediatek: add missing cpu mux causing Mediatek cpufreq can't work") Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-17clk: gemini: Fix reset regressionLinus Walleij
commit e2860e1f62f2 ("serial: 8250_of: Add reset support") introduced reset support for the 8250_of driver. However it unconditionally uses the assert/deassert pair to deassert reset on the device at probe and assert it at remove. This does not work with systems that have a self-deasserting reset controller, such as Gemini, that recently added a reset controller. As a result, the console will not probe on the Gemini with this message: Serial: 8250/16550 driver, 1 ports, IRQ sharing disabled of_serial: probe of 42000000.serial failed with error -524 This (-ENOTSUPP) is the error code returned by the deassert() operation on self-deasserting reset controllers. To work around this, implement dummy .assert() and .deassert() operations in the Gemini combined clock and reset controller. This fixes the issue on this system. Cc: Joel Stanley <joel@jms.id.au> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: linux-serial@vger.kernel.org Fixes: e2860e1f62f2 ("serial: 8250_of: Add reset support") Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-17clk: vc5: Add support for IDT VersaClock 5P49V5925Vladimir Barinov
Update IDT VersaClock 5 driver to support 5P49V5925. This chip has only external clock input, four fractional dividers (FODs) and five clock outputs (four universal clock outputs and one reference clock output at OUT0_SELB_I2C). Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com> Reviewed-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-17clk: vc5: Add support for IDT VersaClock 5P49V6901Marek Vasut
Update IDT VersaClock 5 driver to support IDT VersaClock 6 5P49V6901. This chip has two clock inputs (external XTAL or external CLKIN), four fractional dividers (FODs) and five clock outputs (four universal clock outputs and one reference clock output at OUT0_SELB_I2C). Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Alexey Firago <alexey_firago@mentor.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: linux-renesas-soc@vger.kernel.org Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> on Salvator-XS with the display LVDS output. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-17clk: vc5: Add support for the input frequency doublerMarek Vasut
The VersaClock 6 has an input frequency doubler between the input clock mux and the predivider. Add new capability flag and support for this frequency doubler block into the driver. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Alexey Firago <alexey_firago@mentor.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: linux-renesas-soc@vger.kernel.org Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> on Salvator-XS with the display LVDS output. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-17clk: vc5: Split clock input mux and predividerMarek Vasut
Split the VC5 clock input mux and the predivider to more accurately model the hardware and fix the previously incorrect assumption that both the OUT_SEL_I2CB and the PLL are fed from the predivider. It is in fact the clock input mux output which is directly feeding the clock into the OUT_SEL_I2CB output, while the clock input mux output first passes through the predivider before it is fed into the PLL. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Alexey Firago <alexey_firago@mentor.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: linux-renesas-soc@vger.kernel.org Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> on Salvator-XS with the display LVDS output. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-17clk: vc5: Configure the output buffer input mux on prepareMarek Vasut
The output buffer input mux can be configured in either of three states -- disabled, input from FOD, input from previous output. Once the .prepare() callback of the output buffer is called, the output buffer input mux must be set to either input from FOD or input from previous output, it cannot be set to Disabled anymore or the output won't work. Default to the input from FOD if the output buffer input mux was Disabled and the .prepare() was called on it. Note that we do not set the output buffer input mux back to Disabled in the .unprepare() callback as there is no obvious benefit of doing so. We disable the entire output buffer in the .unprepare() callback already. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Alexey Firago <alexey_firago@mentor.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: linux-renesas-soc@vger.kernel.org Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> # Salvator-XS with the display LVDS output. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-17clk: vc5: Do not warn about disabled output buffer input muxesMarek Vasut
The output buffer input mux can be configured in either of three states -- disabled, input from FOD, input from previous output. If the output buffer input mux is set to disabled, the code in vc5_clk_out_get_parent() would consider this an invalid setting and warn about it, which is not necessarily the case. In case the output buffer input mux is disabled, default to input from FOD to have some parent and don't print the warning. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Alexey Firago <alexey_firago@mentor.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: linux-renesas-soc@vger.kernel.org Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> # Salvator-XS with the display LVDS output. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-17clk: vc5: Fix trivial typoMarek Vasut
Fix trivial typo in vc5_clk_out_unprepare() , s/Enable/Disable/ . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Alexey Firago <alexey_firago@mentor.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: linux-renesas-soc@vger.kernel.org Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> # Salvator-XS with the display LVDS output. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-17clk: vc5: Prevent division by zero on unconfigured outputsMarek Vasut
In case the initial values of the FOD registers are not configured in the OTP or by the bootloader, it is possible that the FOD registers will contain zeroes. The code in vc5_fod_recalc_rate() immediately feeds the FOD divider value obtained from the FOD registers into the div64_u64() and if the FOD divider value is zero, triggers division by zero exception. Check if the FOD divider value is zero and return the frequency of the FOD output as 0 Hz if it is so. This prevents the division by zero exception. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Alexey Firago <alexey_firago@mentor.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: linux-renesas-soc@vger.kernel.org Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> # Salvator-XS with the display LVDS output. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-17clk: axs10x: introduce AXS10X pll driverEugeniy Paltsev
AXS10X boards manages it's clocks using various PLLs. These PLL has same dividers and corresponding control registers mapped to different addresses. So we add one common driver for such PLLs. Each PLL on AXS10X board consist of three dividers: IDIV, FBDIV and ODIV. Output clock value is managed using these dividers. We add pre-defined tables with supported rate values and appropriate configurations of IDIV, FBDIV and ODIV for each value. As of today we add support for PLLs that generate clock for the following devices: * ARC core on AXC CPU tiles. * ARC PGU on ARC SDP Mainboard. and more to come later. By this patch we add support for two plls (arc core pll and pgu pll), so we had to use two different init types: CLK_OF_DECLARE for arc core pll and regular probing for pgu pll. Acked-by: Rob Herring <robh@kernel.org> Acked-by: Jose Abreu <joabreu@synopsys.com> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com> Signed-off-by: Jose Abreu <joabreu@synopsys.com> [sboyd@codeaurora.org: Silence dubious !x & y sparse warning, make of_axs10x_pll_clk_setup() unregister clk on failure] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-15Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds
Pull MIPS updates from Ralf Baechle: "Boston platform support: - Document DT bindings - Add CLK driver for board clocks CM: - Avoid per-core locking with CM3 & higher - WARN on attempt to lock invalid VP, not BUG CPS: - Select CONFIG_SYS_SUPPORTS_SCHED_SMT for MIPSr6 - Prevent multi-core with dcache aliasing - Handle cores not powering down more gracefully - Handle spurious VP starts more gracefully DSP: - Add lwx & lhx missaligned access support eBPF: - Add MIPS support along with many supporting change to add the required infrastructure Generic arch code: - Misc sysmips MIPS_ATOMIC_SET fixes - Drop duplicate HAVE_SYSCALL_TRACEPOINTS - Negate error syscall return in trace - Correct forced syscall errors - Traced negative syscalls should return -ENOSYS - Allow samples/bpf/tracex5 to access syscall arguments for sane traces - Cleanup from old Kconfig options in defconfigs - Fix PREF instruction usage by memcpy for MIPS R6 - Fix various special cases in the FPU eulation - Fix some special cases in MIPS16e2 support - Fix MIPS I ISA /proc/cpuinfo reporting - Sort MIPS Kconfig alphabetically - Fix minimum alignment requirement of IRQ stack as required by ABI / GCC - Fix special cases in the module loader - Perform post-DMA cache flushes on systems with MAARs - Probe the I6500 CPU - Cleanup cmpxchg and add support for 1 and 2 byte operations - Use queued read/write locks (qrwlock) - Use queued spinlocks (qspinlock) - Add CPU shared FTLB feature detection - Handle tlbex-tlbp race condition - Allow storing pgd in C0_CONTEXT for MIPSr6 - Use current_cpu_type() in m4kc_tlbp_war() - Support Boston in the generic kernel Generic platform: - yamon-dt: Pull YAMON DT shim code out of SEAD-3 board - yamon-dt: Support > 256MB of RAM - yamon-dt: Use serial* rather than uart* aliases - Abstract FDT fixup application - Set RTC_ALWAYS_BCD to 0 - Add a MAINTAINERS entry core kernel: - qspinlock.c: include linux/prefetch.h Loongson 3: - Add support Perf: - Add I6500 support SEAD-3: - Remove GIC timer from DT - Set interrupt-parent per-device, not at root node - Fix GIC interrupt specifiers SMP: - Skip IPI setup if we only have a single CPU VDSO: - Make comment match reality - Improvements to time code in VDSO" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (86 commits) locking/qspinlock: Include linux/prefetch.h MIPS: Fix MIPS I ISA /proc/cpuinfo reporting MIPS: Fix minimum alignment requirement of IRQ stack MIPS: generic: Support MIPS Boston development boards MIPS: DTS: img: Don't attempt to build-in all .dtb files clk: boston: Add a driver for MIPS Boston board clocks dt-bindings: Document img,boston-clock binding MIPS: Traced negative syscalls should return -ENOSYS MIPS: Correct forced syscall errors MIPS: Negate error syscall return in trace MIPS: Drop duplicate HAVE_SYSCALL_TRACEPOINTS select MIPS16e2: Provide feature overrides for non-MIPS16 systems MIPS: MIPS16e2: Report ASE presence in /proc/cpuinfo MIPS: MIPS16e2: Subdecode extended LWSP/SWSP instructions MIPS: MIPS16e2: Identify ASE presence MIPS: VDSO: Fix a mismatch between comment and preprocessor constant MIPS: VDSO: Add implementation of gettimeofday() fallback MIPS: VDSO: Add implementation of clock_gettime() fallback MIPS: VDSO: Fix conversions in do_monotonic()/do_monotonic_coarse() MIPS: Use current_cpu_type() in m4kc_tlbp_war() ...
2017-07-11clk: boston: Add a driver for MIPS Boston board clocksPaul Burton
Add a driver for the clocks provided by the MIPS Boston board from Imagination Technologies. 2 clocks are provided - the system clock & the CPU clock - and each is a simple fixed rate clock whose frequency can be determined by reading a register provided by the board. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: James Hogan <james.hogan@imgtec.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: linux-clk@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16483/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-06-29clk: gemini: Read status before using the valueJoel Stanley
The probe does a shift and mask of val without having read it from the hardware. Fixes: 846423f96721 ("clk: Add Gemini SoC clock controller") Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-29clk: scpi: error when clock fails to registerJerome Brunet
Current implementation of scpi_clk_add just print a warning when clock fails to register but then keep going as if nothing happened. The provider is then registered with bogus data. This may latter lead to an Oops in __clk_create_clk when hlist_add_head(&clk->clks_node, &hw->core->clks) is called. This patch fixes the issue and errors if a clock fails to register. Fixes: cd52c2a4b5c4 ("clk: add support for clocks provided by SCP(System Control Processor)") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-29clk: at91: Add sama5d2 suspend/resumeAlexandre Belloni
On sama5d2, VDD core maybe be cut while in suspend. This means registers will be lost. Ensure they are saved and restored properly. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-22clk: keystone: TI_SCI_PROTOCOL is needed for clk driverArnd Bergmann
CONFIG_COMPILE_TEST allows building a configuration without TI_SCI_PROTOCOL, which then fails to link: drivers/clk/keystone/sci-clk.o: In function `ti_sci_clk_probe': sci-clk.c:(.text.ti_sci_clk_probe+0x4c): undefined reference to `devm_ti_sci_get_handle' This makes it a hard dependency. Right now, that means we can't actually compile-test the driver unless ARCH_KEYSTONE is set as well, but we can fix that by allowing TI_MESSAGE_MANAGER to be selected for COMPILE_TEST as well. Fixes: b745c0794e2f ("clk: keystone: Add sci-clk driver support") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-22clk: samsung: audss: Fix silent hang on Exynos4412 due to disabled EPLLKrzysztof Kozlowski
Similarly to commit f1e9203e2366 ("clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable failure due to domain being gated") for Exynos5420, the Exynos4412 also requires that EPLL is not disabled. Otherwise any access to MAUDIO block will silently halt. This was not visible before because EPLL on Exynos4 could not be disabled before commit 6edfa11cb396 ("clk: samsung: Add enable/disable operation for PLL36XX clocks"). After this commit, on Odroid U3 board one can see silent hang, usually with last (but unrelated) messages: [ 2.382741] input: gpio_keys as /devices/platform/gpio_keys/input/input0 [ 2.405686] usb 1-3: new high-speed USB device number 3 using exynos-ehci [ 2.419843] max77686-rtc max77686-rtc: setting system clock to 2017-06-21 17:04:13 UTC (1498064653) Mark Exynos4 variant as also needed EPLL to be enabled all the time. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-21clk: uniphier: provide NAND controller clock rateMasahiro Yamada
This allows the NAND driver to get the clock rate via clk_get_rate(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-21clk: hisilicon: add usb2 clocks for hi3798cv200 SoCJiancheng Xue
Add usb2 clocks for hi3798cv200 SoC. Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-21clk: Add Gemini SoC clock controllerLinus Walleij
The Cortina Systems Gemini (SL3516/CS3516) has an on-chip clock controller that derive all clocks from a single crystal, using some documented and some undocumented PLLs, half dividers, counters and gates. This is a best attempt to construct a clock driver for the clocks so at least we can gate off unused hardware and driver the PCI bus clock. Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> [sboyd@codeaurora.org: Fix devm_ioremap_resource() return value checking] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-21clk: iproc: Remove __init marking on iproc_pll_clk_setup()Stephen Boyd
Now that this function is called from driver probe routines, it needs to drop the __init marking because it isn't just called from init code. Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Cc: Sandeep Tripathy <sandeep.tripathy@broadcom.com> Cc: Anup Patel <anup.patel@broadcom.com> Cc: Ray Jui <ray.jui@broadcom.com> Cc: Scott Branden <scott.branden@broadcom.com> Fixes: 654cdd3229cd ("clk: bcm: Add clocks for Stingray SOC") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19clk: bcm: Add clocks for Stingray SOCSandeep Tripathy
This patch adds support for Stingray clocks in iproc ccf. The Stingray SOC has various plls based on iproc pll architecture. Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com> Signed-off-by: Anup Patel <anup.patel@broadcom.com> Reviewed-by: Ray Jui <ray.jui@broadcom.com> Reviewed-by: Scott Branden <scott.branden@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19clk: mediatek: export cpu multiplexer clock for MT8173 SoCsSean Wang
The patch enables CPU multiplexer clock on MT8173 SoC which fixes up cpufreq driver fails at acquiring intermediate clock source when driver probe is called. Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19clk: mediatek: export cpu multiplexer clock for MT2701/MT7623 SoCsSean Wang
The patch enables CPU multiplexer clock on MT2701/MT7623 SoC which fixes up cpufreq driver fails at acquiring intermediate clock source when driver probe is called. Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19clk: mediatek: add missing cpu mux causing Mediatek cpufreq can't workSean Wang
This patch adds CPU multiplexer clocks which are essential for Mediatek cpufreq driver. It would use the CPU clock multiplexer to switch to the intermediate clock source temporarily and then wait for the primary clock changing getting stable. Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19clk: renesas: cpg-mssr: Use of_device_get_match_data() helperGeert Uytterhoeven
If CONFIG_OF=n: drivers/clk/renesas/renesas-cpg-mssr.c: In function ‘cpg_mssr_probe’: drivers/clk/renesas/renesas-cpg-mssr.c:702: warning: dereferencing ‘void *’ pointer drivers/clk/renesas/renesas-cpg-mssr.c:702: error: request for member ‘data’ in something not a structure or union To fix this, use the of_device_get_match_data() helper, for which a dummy version is provided if CONFIG_OF=n. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19clk: hi6220: add acpu clockZhangfei Gao
Add acpu clock, including sft clock controlling hi6220 coresight module Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Li Pengcheng <lipengcheng8@huawei.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19clk: zx296718: export I2S mux clocksShawn Guo
Export I2S mux clocks, so that device tree can refer to them for setting a better parent clock for I2S work clock. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19clk: imx7d: create clocks behind rawnand clock gateStefan Agner
The rawnand clock gate gates two clocks, NAND_USDHC_BUS_CLK_ROOT and NAND_CLK_ROOT. However, the gate has been in the chain of the latter only. This does not allow to use the NAND_USDHC_BUS_CLK_ROOT only, e.g. as required by APBH-Bridge-DMA. Add new clocks which represent the clock after the gate, and use a shared clock gate to correctly model the hardware. Signed-off-by: Stefan Agner <stefan@agner.ch> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Han Xu <han.xu@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19clk: hi3660: Set PPLL2 to 2880MZhong Kaihua
Set PPLL2 to 2880M. With this patch, we saw better compatibility on various 1080p HDMI monitors. Signed-off-by: Zhong Kaihua <zhongkaihua@huawei.com> Signed-off-by: Zheng Shaobo <zhengshaobo1@huawei.com> Acked-by: Zhangfei Gao <zhangfei.gao@linaro.org> [sboyd@codeaurora.org: Add UL to long number to silence C90 warning] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19clk: hi3660: add clocks for video encoder, decoder and ISPChen Jun
This patch adds more clocks for hi3660, including: - video encoder and decoder - ISP (Image Signal Processing) Signed-off-by: Chen Jun <chenjun14@huawei.com> Signed-off-by: Zhong Kaihua <zhongkaihua@huawei.com> Signed-off-by: Guodong Xu <guodong.xu@linaro.org> Reviewed-by: Zhangfei Gao <zhangfei.gao@linaro.org> Acked-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19clk: hi3660: fix wrong parent name of clk_mux_sysbusChen Jun
Parent name of clk_mux_sysbus is not correct. This patch fixes it. Signed-off-by: Chen Jun <chenjun14@huawei.com> Signed-off-by: John Stultz <john.stultz@linaro.org> Signed-off-by: Guodong Xu <guodong.xu@linaro.org> Acked-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19clk: gcc-msm8916: add support to 9.6MHz codec clkSrinivas Kandagatla
MCLK for internal audio codec is expected to be at 9.6MHz by default. This patch adds support to 9.6MHz to make the default case possible. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19clk: qcom: Add ipq8074 Global Clock Controller supportAbhishek Sahu
This patch adds support for the global clock controller found on the ipq8074 based devices. This includes UART, I2C, SPI etc. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19clk: mvebu: cp110: Minor cleanupsStephen Boyd
Mark an array of strings static const and remove the dereference of a function pointer when assigning to the platform driver probe struct member. drivers/clk/mvebu/cp110-system-controller.c:89:12: warning: symbol 'gate_base_names' was not declared. Should it be static? drivers/clk/mvebu/cp110-system-controller.c:447:18: error: cannot dereference this type Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19Merge branch 'clk-cp110' of git://git.infradead.org/linux-mvebu into clk-nextStephen Boyd
Pull improved Marvel Armada 7K/8K cp110 clk support from Gregory CLEMENT: We got more information about the clock controllers and the clock tree of the CP110 part that we find in the Marvell Armada 7K/8K SoCs. The clk driver is modified accordingly from this new information. * 'clk-cp110' of git://git.infradead.org/linux-mvebu: clk: mvebu: cp110: add sdio clock to cp-110 system controller clk: mvebu: cp110: introduce a new binding clk: mvebu: cp110: do not depend anymore of the *-clock-output-names clk: mvebu: cp110: make failure labels more meaningful
2017-06-19clk: socfpga: Fix the smplsel on Arria10 and Stratix10Dinh Nguyen
The smplsel bits for the SDMMC clock on Arria10 and Stratix10 platforms are offset by 1 additional bit. Add a new macro SYSMGR_SDMMC_CTRL_SET_AS10 for usage on the Arria10 and Stratix10 platforms. Fixes: 5611a5ba8e54 ("clk: socfpga: update clk.h so for Arria10 platform to use") Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19clk: Hi3660: register fixed_rate_clks with CLK_OF_DECLARE_DRIVERLeo Yan
The timer will register into system at very early phase at kernel boot; if timer needs to use clock, the clock should be get ready in function of_clk_init() so later the timer driver probe can retrieve clock successfully. This is finished in below flow on arm64: start_kernel() `-> time_init() `-> of_clk_init(NULL) => register timer's clock `-> clocksource_probe() => register timer On Hi3660 the sp804 timer uses clock "osc32k", this clock is registered as platform driver rather than CLK_OF_DECLARE_DRIVER method. As result, sp804 timer probe returns failure due if cannot bind clock properly. To fix the failure, this patch is to split crgctrl clocks into two subsets. One part is for fixed_rate_clks which includes pre-defined fixed rate clocks, and "osc32k" clock is in this category; So we change their registration to CLK_OF_DECLARE_DRIVER method, as result the clocks can be registered ahead with function of_clk_init() and timer driver can bind timer clock successfully; the rest of the crgctrl clocks are still registered by the probe of the platform driver. This patch also adds checking for all crgctrl clocks registration and print out log if any clock has failure. Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19clk: mvebu: cp110: add sdio clock to cp-110 system controllerKonstantin Porotchkin
This commit updates the CP110 system controller driver to add the definition for a missing clock. The SDIO clock is dedicated driving the SDHCI interface and its frequency is 400MHz (2/5 of PLL source clock). The SDIO interface should be bound to this clock and not the core clock as in the older code. Using the wrong clock lead to a maximum SDHCI frequency of 250 Mhz, while the HW really supports up to 400 Mhz. This patch also fixes the NAND clock relationship documentation. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> [gregory.clement@free-electrons.com: - use sdio instead of emmc to name the clock] Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-06-19clk: mvebu: cp110: introduce a new bindingGregory CLEMENT
The initial intent when the binding of the cp110 system controller was to have one flat node. The idea being that what is currently a clock-only driver in drivers would become a MFD driver, exposing the clock, GPIO and pinctrl functionality. However, after taking a step back, this would lead to a messy binding. Indeed, a single node would be a GPIO controller, clock controller, pinmux controller, and more. This patch adopts a more classical solution of a top-level syscon node with sub-nodes for the individual devices. The main benefit will be to have each functional block associated to its own sub-node where we can put its own properties. The introduction of the Armada 7K/8K is still in the early stage so the plan is to remove the old binding. However, we don't want to break the device tree compatibility for the few devices already in the field. For this we still keep the support of the legacy compatible string with a big warning in the kernel about updating the device tree. Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-06-19clk: mvebu: cp110: do not depend anymore of the *-clock-output-namesGregory CLEMENT
Using the *-clock-output-names property was a convenient way to have a unique name for each clock even when there are multiple cp110 blocks as we can find on Armada 8K. However it has some drawbacks: the main one being a stronger link than necessary between the driver and the device tree. For example the clock name can't be changed, removed or moved. It is still the early stage of introduction of the Armada 7K/8K and the hardware is still not totally documented, especially for the clock part. By removing the use of *-clock-output-names it will be easier to add new clocks without breaking the compatibility. The name of each clock is now created by using its physical address as a prefix (as it was done for the platform device names). Thanks to this we have an automatic way to compute a unique name. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-04 13:24:55 +0000