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2016-12-02arm/arm64: xen: Move shared architecture headers to include/xen/armMarc Zyngier
ARM and arm64 Xen ports share a number of headers, leading to packaging issues when these headers needs to be exported, as it breaks the reasonable requirement that an architecture port has self-contained headers. Fix the issue by moving the 5 header files to include/xen/arm, and keep local placeholders to include the relevant files. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
2016-12-02ARM64: dts: marvell: Add network support for Armada 3700Gregory CLEMENT
Add neta nodes for network support both in device tree for the SoC and the board. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2016-12-02arm64: dts: juno: fix cluster sleep state entry latency on all SoC versionsSudeep Holla
The core and the cluster sleep state entry latencies can't be same as cluster sleep involves more work compared to core level e.g. shared cache maintenance. Experiments have shown on an average about 100us more latency for the cluster sleep state compared to the core level sleep. This patch fixes the entry latency for the cluster sleep state. Fixes: 28e10a8f3a03 ("arm64: dts: juno: Add idle-states to device tree") Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: "Jon Medhurst (Tixy)" <tixy@linaro.org> Reviewed-by: Liviu Dudau <Liviu.Dudau@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-12-02arm64: Get rid of asm/opcodes.hMarc Zyngier
The opcodes.h drags in a lot of definition from the 32bit port, most of which is not required at all. Clean things up a bit by moving the bare minimum of what is required next to the actual users, and drop the include file. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-12-02arm64: smp: Prevent raw_smp_processor_id() recursionRobin Murphy
Under CONFIG_DEBUG_PREEMPT=y, this_cpu_ptr() ends up calling back into raw_smp_processor_id(), resulting in some hilariously catastrophic infinite recursion. In the normal case, we have: #define this_cpu_ptr(ptr) raw_cpu_ptr(ptr) and everything is dandy. However for CONFIG_DEBUG_PREEMPT, this_cpu_ptr() is defined in terms of my_cpu_offset, wherein the fun begins: #define my_cpu_offset per_cpu_offset(smp_processor_id()) ... #define smp_processor_id() debug_smp_processor_id() ... notrace unsigned int debug_smp_processor_id(void) { return check_preemption_disabled("smp_processor_id", ""); ... notrace static unsigned int check_preemption_disabled(const char *what1, const char *what2) { int this_cpu = raw_smp_processor_id(); and bang. Use raw_cpu_ptr() directly to avoid that. Fixes: 57c82954e77f ("arm64: make cpu number a percpu variable") Reported-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Robin Murphy <robin.murphy@arm.com> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-12-02arm64/cpuinfo: Convert to hotplug state machineAnna-Maria Gleixner
Install the callbacks via the state machine and let the core invoke the callbacks on the already online CPUs. Signed-off-by: Anna-Maria Gleixner <anna-maria@linutronix.de> Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: rt@linutronix.de Cc: linux-arm-kernel@lists.infradead.org Link: http://lkml.kernel.org/r/20161126231350.10321-17-bigeasy@linutronix.de Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2016-12-02arm64/cpuinfo: Make hotplug notifier symmetricAnna-Maria Gleixner
There is no requirement to keep the sysfs files around until the CPU is completely dead. Remove them during the DOWN_PREPARE notification. This is a preparatory patch for converting to the hotplug state machine. Signed-off-by: Anna-Maria Gleixner <anna-maria@linutronix.de> Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: rt@linutronix.de Cc: linux-arm-kernel@lists.infradead.org Link: http://lkml.kernel.org/r/20161126231350.10321-16-bigeasy@linutronix.de Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2016-12-02ACPI / APEI / ARM64: APEI initial support for ARM64Tomasz Nowicki
This patch provides APEI arch-specific bits for ARM64 Meanwhile, (1) Move HEST type (ACPI_HEST_TYPE_IA32_CORRECTED_CHECK) checking to a generic place. (2) Select HAVE_ACPI_APEI when EFI and ACPI is set on ARM64, because arch_apei_get_mem_attribute is using efi_mem_attributes() on ARM64. Signed-off-by: Tomasz Nowicki <tomasz.nowicki@linaro.org> Tested-by: Jonathan (Zhixiong) Zhang <zjzhang@codeaurora.org> Signed-off-by: Fu Wei <fu.wei@linaro.org> [ Fu Wei: improve && upstream ] Acked-by: Hanjun Guo <hanjun.guo@linaro.org> Tested-by: Tyler Baicar <tbaicar@codeaurora.org> Acked-by: Will Deacon <will.deacon@arm.com> Reviewed-by: Borislav Petkov <bp@suse.de> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2016-12-01crypto: arm64/aes-ce-ccm - Fix AEAD decryption lengthHerbert Xu
This patch fixes the ARM64 CE CCM implementation decryption by using skcipher_walk_aead_decrypt instead of skcipher_walk_aead, which ensures the correct length is used when doing the walk. Fixes: cf2c0fe74084 ("crypto: aes-ce-ccm - Use skcipher walk interface") Reported-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-11-30arm64: dts: juno: Correct PCI IO windowJeremy Linton
The PCIe root complex on Juno translates the MMIO mapped at 0x5f800000 to the PIO address range starting at 0 (which is common because PIO addresses are generally < 64k). Correct the DT to reflect this. Signed-off-by: Jeremy Linton <jeremy.linton@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-11-30Merge tag 'amlogic-dt64-2-v2' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/dt64 Pull "Amlogic 64-bit DT updates for v4.10, round 2" from Kevin Hilman: - new SoC support: S912/GXM series (8x A53) - new boards: Nexbox A1 (S912), Nexbox A95X (S905X) - resets for 2nd USB PHY - update SCPI compatible for pre-v1.0 devices * tag 'amlogic-dt64-2-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: ARM64: dts: meson-gxbb: add SCPI pre-1.0 compatible ARM64: dts: meson-gxl: Add support for Nexbox A95X ARM64: dts: meson-gxm: Add support for the Nexbox A1 ARM64: dts: Add support for Meson GXM ARM64: dts: meson-gxbb: add the USB reset also to the second USB PHY
2016-11-30Merge tag 'zte-dt64-4.10' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt64 Pull "ZTE arm64 device tree update for 4.10" from Shawn Guo: Add clock controller device nodes, including one top clock controller, two low speed clock controllers and one audio clock controller. * tag 'zte-dt64-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: arm64: dts: zx: Add clock controller nodes
2016-11-30Merge tag 'berlin64-dt-for-v4.10-1' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/jszhang/linux-berlin into next/dt64 Pull "Berlin64 DT changes for v4.10" from Jisheng Zhang: - fix some dtc compiler warnings * tag 'berlin64-dt-for-v4.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/jszhang/linux-berlin: arm64: dts: berlin4ct-dmp: add missing unit name to /memory node arm64: dts: berlin4ct-stb: add missing unit name to /memory node arm64: dts: berlin4ct: add missing unit name to /soc node
2016-11-30Merge tag 'v4.10-rockchip-dts64-2' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt64 Pull "Rockchip dts64 changes for 4.10" from Heiko Stübner: Some more powerdomains and usb2-otg support for the rk3399 as well as the binding doc for the 32bit rk1108 eval board to prevent it from conflicting with the recently added 64bit px5 board. * tag 'v4.10-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: dt-bindings: add rockchip RK1108 Evaluation board arm64: dts: rockchip: add usb2-phy otg-port support for rk3399 arm64: dts: rockchip: add pd_sd power-domain node for rk3399 arm64: dts: rockchip: add eMMC's power domain support for rk3399 arm64: dts: rockchip: add backlight support for rk3399 evb board arm64: dts: rockchip: add gmac needed pclk for rk3399 pd
2016-11-30Merge tag 'v4.10-rockchip-defconfig64' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/arm64 Pull "Rockchip defconfig64 changes for 4.10" from Heiko Stübner: 64bit defconfig changes to allow arm64 Rockchip socs to basically boot. * tag 'v4.10-rockchip-defconfig64' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: arm64: defconfig: allow rk3399-based boards to boot from mmc and usb arm64: defconfig: enable RK808 components arm64: defconfig: enable I2C and DW MMC controller on rockchip platform
2016-11-30arm64: defconfig: drop GPIO_SYSFS on multiplatformsLinus Walleij
The sysfs ABI to GPIO is marked obsolete and should not be encouraged. Users should be encouraged to switch to using the character device. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-11-30Merge tag 'qcom-arm64-for-4.10-2' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/dt64 Pull "Qualcomm ARM64 Updates for v4.10 - Part 2" from Andy Gross: * Add SDHC xo clk and 1.8V DDR support * tag 'qcom-arm64-for-4.10-2' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux: arm64: dts: qcom: msm8916: Add ddr support to sdhc1 ARM: dts: Add xo to sdhc clock node on qcom platforms
2016-11-30Merge tag 'samsung-dt64-4.10-2' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt64 Pull "Samsung DeviceTree arm64 second update for v4.10" from Krzysztof Kozłowski: 1. Add Performance Monitor Unit to Exynos7. 2. Add MFC, JPEG and Gscaler to Exynos5433 based TM2 board. 3. Cleanups and fixes for recently added TM2 and TM2E boards. * tag 'samsung-dt64-4.10-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: arm64: dts: exynos: Enable HS400 mode for eMMC for TM2 arm64: dts: exynos: Add the mshc_2 node for supporting T-Flash arm64: dts: exynos: TM2 - add support for MFC video codec device arm64: dts: exynos: TM2 - add support for JPEG codec device arm64: dts: exynos: TM2 - add support for GScaler devices arm64: dts: exynos: TM2 - remove unused UART3 and set clocks directly on CMU arm64: dts: exynos: Assign parent clock of the clkout clock for TM2 board arm64: dts: exynos: Move FSYS CMU configuration from Exynos5433 dtsi to TM2 dts arm64: dts: exynos: Add missing parent clocks to audio block in Exynos5433 SoC arm64: dts: exynos: Fix FSYS CMU parent clocks in Exynos5433 SoC arm64: dts: exynos: Fix IRQ type flags for Exynos5433 SoC arm64: dts: Add ARM PMU node for exynos7
2016-11-30Merge tag 'arm-soc/for-4.10/defconfig-arm64' of ↵Arnd Bergmann
http://github.com/Broadcom/stblinux into next/arm64 Pull "Broadcom defconfig-arm64 changes for 4.10" from Florian Fainelli: This pull request contains Broadcom ARM64-based SoCs defconfig changes for 4.10, please pull the following changes: - Eric updates the ARMv8 defconfig to contain everything that is needed to run a 64-bit kernel on the Raspberry Pi 3 - Scott enables the standard AT25 EEPROM driver as module for the ARM64 defconfig - Martin enables the Raspberry Pi Thermal driver in the ARM64 defconfig * tag 'arm-soc/for-4.10/defconfig-arm64' of http://github.com/Broadcom/stblinux: ARM64: bcm2835: add thermal driver to default config arm64: defconfig: enable EEPROM_AT25 config option arm64: Add BCM2835 (Raspberry Pi 3) support to the defconfig
2016-11-30Merge tag 'arm-soc/for-4.10/devicetree-arm64' of ↵Arnd Bergmann
http://github.com/Broadcom/stblinux into next/dt64 Pull "Broadcom devicetree-arm64 changes for 4.10" from Florian Fainelli: This pull request contains Broadcom ARM64 based SoC Device Tree changes for 4.10, please pull the following: - Robin updates the Northstart 2 DTS to use the generic IOMMU binding - Scott renames the Broadcom Northstar 2 binding document to use a standard name including the brcm vendor prefix - Kamal adds the QSPI Device Tree node to the Northstar 2 SoC and updates the Northstar 2 SVK reference board DTS file with it enabled. - Rob adds the Device Tree node for the Broadcom PDC (mailbox) hardware to the Northstar 2 SoC - Jon enables the SDIO1 block and adds proper PCIe PHYs Device Tree nodes to the Northstar 2 SoC - Ray adds required properties NAND controller properties to make NAND work on the Northstar 2 SVK board, this was submitted as a 4.9 fixes and is included here to resolve DTS file merges - Andrea removes an incorrect power LED from the Raspberry Pi 3 DTS - Andreas fixes the compatible string for the BCM2837 (Raspberry Pi 3) - Eric defines standard pinctrl groups in the BCM2835 GPIO node - Gerd adds definitions for the pinctrl groups and updates the PWM, I2C and SDHCI nodes to use their appropriate pinctrl functions - Linus adds names for the Raspberry Pi GPIO lines based on the datasheet - Martin adds the DT binding and nodes for the Raspberry Pi firmware thermal block - Stefan fixes a few typos with respect to the BCM2835 mailbox binding example and Device Tree nodes he also uses the proper DTSI file to define the USB host mode for the USB Device Tree nodes * tag 'arm-soc/for-4.10/devicetree-arm64' of http://github.com/Broadcom/stblinux: (23 commits) arm64: dts: NS2: Add PCI PHYs arm64: dts: NS2: enable sdio1 ARM64: dts: bcm2837-rpi-3-b: remove incorrect pwr LED ARM64: bcm2835: dts: add thermal node to device-tree of bcm2837 ARM: bcm2835: Add names for the Raspberry Pi GPIO lines ARM: bcm2835: dts: add thermal node to device-tree of bcm283x dt: bindings: add thermal device driver for bcm2835 arm64: dts: Add Broadcom Northstar2 device tree entries for PDC driver. ARM: dts: bcm283x: fix typo in mailbox address DT: binding: bcm2835-mbox: fix address typo in example ARM64: dts: bcm2835: Fix bcm2837 compatible string arm64: dts: Update Broadcom NS2 to generic IOMMU binding arm64: dts: Updated NAND DT properties for NS2 SVK arm64: dts: rename ns2.txt to brcm,ns2.txt ARM64: dts: Add QSPI Device Tree node for NS2 ARM64: dts: bcm283x: Use dtsi for USB host mode ARM: dts: bcm283x: drop alt3 from &gpio ARM: dts: bcm283x: add pinctrl group to &sdhci, drop pins from &gpio ARM: dts: bcm283x: add pinctrl group to &i2c1, drop pins from &gpio ARM: dts: bcm283x: add pinctrl group to &i2c0, drop pins from &gpio ...
2016-11-30Merge tag 'tegra-for-4.10-arm64-dt-numeric-ids' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt64 Pull "arm64: tegra: Device tree changes for v4.10-rc1" from Thierry Reding: This adds initial support for Tegra186, the P3310 processor module as well as the P2771 development board. Not much is functional, but there is enough to boot to an initial ramdisk with debug serial output. * tag 'tegra-for-4.10-arm64-dt-numeric-ids' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: arm64: tegra: Add NVIDIA P2771 board support arm64: tegra: Enable PSCI on P3310 arm64: tegra: Add NVIDIA P3310 processor module support arm64: tegra: Add GPIO controllers on Tegra186 arm64: tegra: Add SDHCI controllers on Tegra186 arm64: tegra: Add I2C controllers on Tegra186 arm64: tegra: Add serial ports on Tegra186 arm64: tegra: Add CPU nodes for Tegra186 arm64: tegra: Add Tegra186 support
2016-11-30arm64: defconfig: Do not lower CONFIG_LOG_BUF_SHIFTGeert Uytterhoeven
The default value of 17 for CONFIG_LOG_BUF_SHIFT is much more suitable than 14. The latter easily leads to lost kernel messages on systems with only one CPU core. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Catalin Marinas <catalin.marinas@arm.com>
2016-11-30Merge tag 'renesas-arm64-dt2-for-v4.10' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt64 Pull "Second Round of Renesas ARM64 Based SoC DT Updates for v4.10" from Simon Horman: Enhancements: * Add device nodes for PRR * Add m3ulcb board * Enable I2C on r8a7796/salvator-x board * Enable SDHI0 on h3ulcb board * tag 'renesas-arm64-dt2-for-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: arm64: dts: r8a7796: Add device node for PRR arm64: dts: r8a7795: Add device node for PRR arm64: dts: h3ulcb: rename SDHI0 pins arm64: dts: h3ulcb: enable SDHI2 arm64: dts: m3ulcb: enable SDHI2 arm64: dts: m3ulcb: enable SDHI0 arm64: dts: m3ulcb: enable WDT arm64: dts: m3ulcb: enable EXTALR clk arm64: dts: m3ulcb: enable GPIO keys arm64: dts: m3ulcb: enable GPIO leds arm64: dts: m3ulcb: enable SCIF clk and pins arm64: dts: m3ulcb: initial device tree arm64: dts: m3ulcb: add M3ULCB board DT bindings arm64: dts: h3ulcb: update header arm64: dts: h3ulcb: update documentation with official board name arm64: dts: r8a7796: salvator-x: enable I2C arm64: dts: r8a7796: Enable I2C DMA arm64: dts: r8a7796: add I2C support
2016-11-30Merge tag 'renesas-soc-match-for-v4.10' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/drivers Merge "Renesas ARM Based SoC Match Updates for v4.10" from Simon Horman: * Identify SoC and register with the SoC bus * tag 'renesas-soc-match-for-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: soc: renesas: Identify SoC and register with the SoC bus ARM: shmobile: Document DT bindings for Product Register Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-11-30arm64: dts: fix build errors from missing dependenciesArnd Bergmann
Two branches were incorrectly sent without having the necessary header file changes. Rather than back those out now, I'm replacing the symbolic names for the clks and resets with the numeric values to get 'make allmodconfig dtbs' back to work. After the header file changes are merged, we can revert this patch. Fixes: 6bc37fa ("arm64: dts: add Allwinner A64 SoC .dtsi") Fixes: 50784e6 ("dts: arm64: db820c: add pmic pins specific dts file") Acked-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-11-30crypto: arm64/aes-ce-ctr - fix skcipher conversionArd Biesheuvel
Fix a missing statement that got lost in the skcipher conversion of the CTR transform. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-11-30crypto: arm/aes-ce - fix broken monolithic buildArd Biesheuvel
When building the arm64 kernel with both CONFIG_CRYPTO_AES_ARM64_CE_BLK=y and CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y configured, the build breaks with the following error: arch/arm64/crypto/aes-neon-blk.o:(.bss+0x0): multiple definition of `aes_simd_algs' arch/arm64/crypto/aes-ce-blk.o:(.bss+0x0): first defined here Fix this by making aes_simd_algs 'static'. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-11-29Merge Will Deacon's for-next/perf branch into for-next/coreCatalin Marinas
* will/for-next/perf: selftests: arm64: add test for unaligned/inexact watchpoint handling arm64: Allow hw watchpoint of length 3,5,6 and 7 arm64: hw_breakpoint: Handle inexact watchpoint addresses arm64: Allow hw watchpoint at varied offset from base address hw_breakpoint: Allow watchpoint of length 3,5,6 and 7
2016-11-29arm64: head.S: Fix CNTHCTL_EL2 access on VHE systemJintack
Bit positions of CNTHCTL_EL2 are changing depending on HCR_EL2.E2H bit. EL1PCEN and EL1PCTEN are 1st and 0th bits when E2H is not set, but they are 11th and 10th bits respectively when E2H is set. Current code is unintentionally setting wrong bits to CNTHCTL_EL2 with E2H set. In fact, we don't need to set those two bits, which allow EL1 and EL0 to access physical timer and counter respectively, if E2H and TGE are set for the host kernel. They will be configured later as necessary. First, we don't need to configure those bits for EL1, since the host kernel runs in EL2. It is a hypervisor's responsibility to configure them before entering a VM, which runs in EL0 and EL1. Second, EL0 accesses are configured in the later stage of boot process. Signed-off-by: Jintack Lim <jintack@cs.columbia.edu> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-11-29irqchip/gic-v3-its: Specialise readq and writeq accessesVladimir Murzin
readq and writeq type of assessors are not supported in AArch32, so we need to specialise them and glue later with series of 32-bit accesses on AArch32 side. Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-11-29irqchip/gic-v3-its: Specialise flush_dcache operationVladimir Murzin
It'd be better to switch to CMA... but before that done redirect flush_dcache operation, so 32-bit implementation could be wired latter. Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-11-29irqchip/gic-v3: Use nops macro for Cavium ThunderX erratum 23154Will Deacon
The workaround for Cavium ThunderX erratum 23154 has a homebrew pipeflush built out of NOP sequences around the read of the IAR. This patch converts the code to use the new nops macro, which makes it a little easier to read. Reviewed-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-11-29irqchip/gic-v3: Convert arm64 GIC accessors to {read,write}_sysreg_sWill Deacon
The GIC system registers are accessed using open-coded wrappers around the mrs_s/msr_s asm macros. This patch moves the code over to the {read,wrote}_sysreg_s accessors instead, reducing the amount of explicit asm blocks in the arch headers. Reviewed-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-11-29ARM64: dts: ls2080a: add device configuration nodeyangbo lu
Add the dts node for device configuration unit that provides general purpose configuration and status for the device. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Scott Wood <oss@buserror.net> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2016-11-29crypto: arm/aes - Select SIMD in KconfigHerbert Xu
The skcipher conversion for ARM missed the select on CRYPTO_SIMD, causing build failures if SIMD was not otherwise enabled. Fixes: da40e7a4ba4d ("crypto: aes-ce - Convert to skcipher") Fixes: 211f41af534a ("crypto: aesbs - Convert to skcipher") Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-11-29crypto: arm64/sha2 - add generated .S files to .gitignoreArd Biesheuvel
Add the files that are generated by the recently merged OpenSSL SHA-256/512 implementation to .gitignore so Git disregards them when showing untracked files. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-11-28ARM64: dts: meson-gxbb: add SCPI pre-1.0 compatibleKevin Hilman
The SCPI driver has an updated compatible to indicate the pre-released (pre v1.0) status of the driver. Since Amlogic used a pre-1.0 version, add that compatible as well. Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2016-11-28ARM64: dts: meson-gxl: Add support for Nexbox A95XNeil Armstrong
The Nexbox A95X exists with a Meson GXBB (S905) Soc or a Meson GXL SoC (S905X). Add the S905X variant which uses the internal PHY instead of an external PHY. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2016-11-28ARM64: dts: meson-gxm: Add support for the Nexbox A1Neil Armstrong
Add support for the Nexbox A1 board based on the Amlogic S912 SoC. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> [khilman: replace '_' in node-names with '-'] Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2016-11-28crypto: arm64/aes - Convert to skcipherHerbert Xu
This patch converts arm64/aes over to the skcipher interface. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-11-28crypto: aes-ce-ccm - Use skcipher walk interfaceHerbert Xu
This patch makes use of the new skcipher walk interface instead of the obsolete blkcipher walk interface. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-11-28crypto: arm64/sha2 - integrate OpenSSL implementations of SHA256/SHA512Ard Biesheuvel
This integrates both the accelerated scalar and the NEON implementations of SHA-224/256 as well as SHA-384/512 from the OpenSSL project. Relative performance compared to the respective generic C versions: | SHA256-scalar | SHA256-NEON* | SHA512 | ------------+-----------------+--------------+----------+ Cortex-A53 | 1.63x | 1.63x | 2.34x | Cortex-A57 | 1.43x | 1.59x | 1.95x | Cortex-A73 | 1.26x | 1.56x | ? | The core crypto code was authored by Andy Polyakov of the OpenSSL project, in collaboration with whom the upstream code was adapted so that this module can be built from the same version of sha512-armv8.pl. The version in this patch was taken from OpenSSL commit 32bbb62ea634 ("sha/asm/sha512-armv8.pl: fix big-endian support in __KERNEL__ case.") * The core SHA algorithm is fundamentally sequential, but there is a secondary transformation involved, called the schedule update, which can be performed independently. The NEON version of SHA-224/SHA-256 only implements this part of the algorithm using NEON instructions, the sequential part is always done using scalar instructions. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2016-11-28Merge 4.9-rc7 into usb-nextGreg Kroah-Hartman
We want the USB fixes in here as well. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2016-11-26Merge tag 'mvebu-dt64-4.10-2' of git://git.infradead.org/linux-mvebu into ↵Arnd Bergmann
next/dt64 Pull "mvebu dt64 for 4.10 (part 2)" from Gregory CLEMENT: Fix DTC warning on Armada 37xx and 7K/8K * tag 'mvebu-dt64-4.10-2' of git://git.infradead.org/linux-mvebu: ARM64: dts: marvell: Fixup memory DT warning for Armada 37xx arm64: dts: marvell: Fixup config-space DT warning For Armada 7K/8K arm64: dts: marvell: Fixup internal-regs DT warning for Armada 37xx
2016-11-25arm64: dts: berlin4ct-dmp: add missing unit name to /memory nodeJisheng Zhang
This patch fixes the following DTC warning with W=1: "Node /memory has a reg or ranges property, but no unit name" Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
2016-11-25arm64: dts: berlin4ct-stb: add missing unit name to /memory nodeJisheng Zhang
This patch fixes the following DTC warning with W=1: "Node /memory has a reg or ranges property, but no unit name" Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
2016-11-25arm64: dts: berlin4ct: add missing unit name to /soc nodeJisheng Zhang
This patch fixes the following DTC warning with W=1: "Node /soc has a reg or ranges property, but no unit name" Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
2016-11-24arm64: dts: qcom: msm8916: Add ddr support to sdhc1Ritesh Harjani
This adds mmc-ddr-1_8v support to DT for sdhc1 of msm8916. Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-11-23soc: renesas: Identify SoC and register with the SoC busGeert Uytterhoeven
Identify the SoC type and revision, and register this information with the SoC bus, so it is available under /sys/devices/soc0/, and can be checked where needed using soc_device_match(). Identification is done using the Product Register or Common Chip Code Register, as declared in DT (PRR only for now), or using a hardcoded fallback if missing. Example: Detected Renesas R-Car Gen2 r8a7791 ES1.0 ... # cat /sys/devices/soc0/{machine,family,soc_id,revision} Koelsch R-Car Gen2 r8a7791 ES1.0 Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-11-23arm64: Remove I-cache invalidation from flush_cache_range()Catalin Marinas
The flush_cache_range() function (similarly for flush_cache_page()) is called when the kernel is changing an existing VA->PA mapping range to either a new PA or to different attributes. Since ARMv8 has PIPT-like D-caches, this function does not need to perform any D-cache maintenance. The I-cache maintenance is already handled via set_pte_at() and flush_cache_range() cannot anyway guarantee that there are no cache lines left after invalidation due to the speculative loads. This patch makes flush_cache_range() a no-op. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-12 07:10:36 +0000