summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2023-06-21phy: usb: Turn off phy when port is in suspendJustin Chen
The COMMONONN bit turns off the PHY when the host controller puts it into suspend state. This can happen during the following... - Nothing is connected to the port - The host controller goes into low power mode whatever due to auto suspend or system suspend. With COMMONONN we also must unset U2_FREECLK_EXISTS since the UTMI clock is fed by the PHY. With these changes we see a power savings of ~12mW when port is in suspend. Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Signed-off-by: Justin Chen <justin.chen@broadcom.com> Link: https://lore.kernel.org/r/1686859578-45242-2-git-send-email-justin.chen@broadcom.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-06-21phy: tegra: xusb: Clear the driver reference in usb-phy devEJ Hsu
For the dual-role port, it will assign the phy dev to usb-phy dev and use the port dev driver as the dev driver of usb-phy. When we try to destroy the port dev, it will destroy its dev driver as well. But we did not remove the reference from usb-phy dev. This might cause the use-after-free issue in KASAN. Fixes: e8f7d2f409a1 ("phy: tegra: xusb: Add usb-phy support") Cc: stable@vger.kernel.org Signed-off-by: EJ Hsu <ejh@nvidia.com> Signed-off-by: Haotien Hsu <haotienh@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Link: https://lore.kernel.org/r/20230609062932.3276509-1-haotienh@nvidia.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-06-21dt-bindings: phy: mxs-usb-phy: add imx8ulp and imx8qm compatibleXu Yang
The imx8ulp and imx8qm are compatible with imx8dxl. This will add such compatible. Signed-off-by: Xu Yang <xu.yang_2@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230613083445.1129137-2-xu.yang_2@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-06-21dt-bindings: phy: mxs-usb-phy: convert to DT schema formatXu Yang
Convert the binding to DT schema format. Besides, this also add clocks, '#phy-cells', phy-3p0-supply and power-domains properties which are not contained in txt file due to txt file lack updates. Signed-off-by: Xu Yang <xu.yang_2@nxp.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230613083445.1129137-1-xu.yang_2@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-05-30dt-bindings: phy: qcom,qmp-usb: fix bindings errorDmitry Baryshkov
Merge two allOf clauses, which sneaked in in two different patches. Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml:109:1: found duplicate key "allOf" with value "[]" (original value: "[]") Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml:109:1: [error] duplication of key "allOf" in mapping (key-duplicates) Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml:109:1: found duplicate key "allOf" with value "[]" (original value: "[]") Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml: ignoring, error parsing file Fixes: 2daece5eb51e ("dt-bindings: phy: qcom,qmp-usb: Drop legacy bindings and move to newer one (SM6115 & QCM2290)") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Link: https://lore.kernel.org/r/20230521195200.11967-1-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-05-24dt-bindings: phy: qcom,qmp-ufs: fix the sc8180x regsVinod Koul
sc8180x ufs phy requires to describe five reg areas for the phy to work, so move the description to the correct place documenting tx, rx lane 1, 2 and pcs. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20230325122444.249507-8-vkoul@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-05-24dt-bindings: phy: qcom,qmp-pcie: fix the sc8180x regsVinod Koul
sc8180x pcie phy requires to describe six reg areas for the phy to work, so move the description to the correct place documenting tx, rx lane 1, 2 and pcs and pcs misc. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20230325122444.249507-4-vkoul@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-05-19phy: mediatek: tphy: add debugfs filesChunfeng Yun
These debugfs files are mainly used to make eye diagram test easier, especially helpful to do HQA test for a new IC without efuse enabled. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/20230513092218.21139-2-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-05-19phy: core: add debugfs filesChunfeng Yun
Add a debugfs root for phy class, and create a debugfs directory under the root when create phy, then phy drivers can add debugfs files. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/20230513092218.21139-1-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-05-19phy: fsl-imx8mp-usb: add support for phy tuningLi Jun
Add USB PHY parameter tuning for USB certifications. Reviewed-by: Haibo Chen <haibo.chen@nxp.com> Signed-off-by: Li Jun <jun.li@nxp.com> [j.zink: ported to v6.3-rc1 from NXP downstream repo + cleanups] Signed-off-by: Johannes Zink <j.zink@pengutronix.de> Link: https://lore.kernel.org/r/20230516-lustige-usb-phy-dinge-v2-2-3383a0de34ac@pengutronix.de Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-05-19dt-bindings: phy: imx8mq-usb: add phy tuning propertiesJohannes Zink
Add optional properties for tuning of usb phy. Signed-off-by: Johannes Zink <j.zink@pengutronix.de> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230516-lustige-usb-phy-dinge-v2-1-3383a0de34ac@pengutronix.de Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-05-19phy: qcom-qmp-combo: Introduce drm_bridgeBjorn Andersson
The QMP combo PHY sits in an of_graph connected between the DisplayPort controller and a USB Type-C connector (or possibly a redriver). The TCPM needs to be able to convey the HPD signal to the DisplayPort controller, but no directly link is provided by DeviceTree so the signal needs to "pass through" the QMP combo phy. Handle this by introducing a drm_bridge which upon initialization finds the next bridge (i.e. the usb-c-connector) and chain this together. This way HPD changes in the connector will propagate to the DisplayPort driver. The connector bridge is resolved lazily, as the TCPM is expected to be able to resolve the typec mux and switch at probe time, so the QMP combo phy will probe before the TCPM. Acked-by: Neil Armstrong <neil.armstrong@linaro.org> Tested-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Tested-by: Abel Vesa <abel.vesa@linaro.org> Tested-by: Steev Klimaszewski <steev@kali.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on HDK8450 Tested-by: Johan Hovold <johan+linaro@kernel.org> # X13s Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Link: https://lore.kernel.org/r/20230515032743.400170-7-quic_bjorande@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-05-19phy: qcom-qmp-combo: Introduce orientation switchingBjorn Andersson
The data lanes of the QMP PHY is swapped in order to handle changing orientation of the USB Type-C cable. Register a typec_switch device to allow a TCPM to configure the orientation. The newly introduced orientation variable is adjusted based on the request, and the initialized components are brought down and up again. To keep track of what parts needs to be cycled new variables to keep track of the individual init_count is introduced. Both the USB and the DisplayPort altmode signals are properly switched. For DisplayPort the controller will after the TCPM having established orientation power on the PHY, so this is not done implicitly, but for USB the PHY typically is kept initialized across the switch, and must therefore then be reinitialized. This is based on initial work by Wesley Cheng. Link: https://lore.kernel.org/r/20201009082843.28503-3-wcheng@codeaurora.org/ Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Tested-by: Abel Vesa <abel.vesa@linaro.org> Tested-by: Steev Klimaszewski <steev@kali.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on HDK8450 Tested-by: Johan Hovold <johan+linaro@kernel.org> # X13s Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Link: https://lore.kernel.org/r/20230515032743.400170-6-quic_bjorande@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-05-19phy: qcom-qmp-combo: Introduce orientation variableBjorn Andersson
In multiple places throughout the driver code has been written in prepration for handling of orientation switching. Introduce a typec_orientation in qmp_combo and fill out the various "placeholders" with the associated logic. By initializing the orientation to "normal" this change has no functional impact, but reduces the size of the upcoming introduction of dynamic orientation switching. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Tested-by: Abel Vesa <abel.vesa@linaro.org> Tested-by: Steev Klimaszewski <steev@kali.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on HDK8450 Tested-by: Johan Hovold <johan+linaro@kernel.org> # X13s Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Link: https://lore.kernel.org/r/20230515032743.400170-5-quic_bjorande@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-05-19phy: qcom-qmp-combo: Extend phy_mutex to all phy_opsBjorn Andersson
The phy core ensures mutual exclusion across the ops for a given phy, but the upcoming introduction of USB Type-C orientation switching might race with the DisplayPort phy operations. So extend the mutual exclusion to cover the remaining ops as well, to avoid concurrent reconfiguration of the hardware. Reported-by: Johan Hovold <johan@kernel.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Link: https://lore.kernel.org/r/20230515032743.400170-4-quic_bjorande@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-05-19phy: qcom-qmp-combo: Move phy_mutex out of com_init/exitBjorn Andersson
With the upcoming introduction of USB Type-C orientation switching the region of mutual exclusion needs to be extended to cover both the common init/exit as well as the individual functions. So move the phy_mutex one step up the stack. Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Tested-by: Abel Vesa <abel.vesa@linaro.org> Tested-by: Steev Klimaszewski <steev@kali.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on HDK8450 Tested-by: Johan Hovold <johan+linaro@kernel.org> # X13s Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Link: https://lore.kernel.org/r/20230515032743.400170-3-quic_bjorande@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-05-19dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp: Add ports and orientation-switchBjorn Andersson
The QMP combo phy can be connected to a TCPM, a USB controller and a DisplayPort controller for handling USB Type-C orientation switching and propagating HPD signals. Extend the binding to allow these connections to be described. Tested-by: Abel Vesa <abel.vesa@linaro.org> Tested-by: Steev Klimaszewski <steev@kali.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on HDK8450 Tested-by: Johan Hovold <johan+linaro@kernel.org> # X13s Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Link: https://lore.kernel.org/r/20230515032743.400170-2-quic_bjorande@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-05-19Merge branch 'fixes' into nextVinod Koul
This brings in the Qcom qmp patch fixes into next as well
2023-05-19dt-bindings: phy: cdns,salvo: add property ↵Frank Li
cdns,usb2-disconnect-threshold-microvolt Add cdns,usb2-disconnect-threshold-microvolt property to address fake USB disconnection issue during enumeration or suspend state for difference platform. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20230517161646.3418250-7-Frank.Li@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-05-19phy: cadence: salvo: Add cdns,usb2-disconnect-threshold-microvolt propertyFrank Li
Add cdns,usb2-disconnect-threshold-microvolt property to address fake USB disconnection issue during enumeration or suspend state for difference platform. Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20230517161646.3418250-6-Frank.Li@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-05-19phy: cadence: salvo: add .set_mode APIPeter Chen
For NXP platform design, the PHY can't know VBUS well, it causes the FSM in controller seeing the disconnection at L1 use case. With .set_mode API introduced, the controller driver could force PHY seeing B Session VALID when it is at the device mode (VBUS is there), and keep FSM working well. Signed-off-by: Peter Chen <peter.chen@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20230517161646.3418250-5-Frank.Li@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-05-19phy: cadence: salvo: add bist fixPeter Chen
Very limited parts may fail to work on full speed mode (both host and device modes) for USB3 port due to higher threshold in full speed receiver of USB2.0 PHY. One example failure symptom is, the enumeration is failed when connecting full speed USB mouse to USB3 port, especially under high temperature. The workaround is to configure threshold voltage value of single ended receiver by setting USB2.0 PHY register AFE_RX_REG5[2:0] to 3'b101. Signed-off-by: Peter Chen <peter.chen@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20230517161646.3418250-4-Frank.Li@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-05-19phy: cadence: salvo: decrease delay value to zero for txvalidPeter Chen
For USB2 L1 use cases, some hosts may start transferring less than 20us after End of Resume, it causes the host seeing corrupt packet from the device side. The reason is the delay time between PHY powers up and txvalid is 20us. To fix it, we change the delay value as 0us. Signed-off-by: Peter Chen <peter.chen@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20230517161646.3418250-3-Frank.Li@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-05-19phy: cadence: salvo: add access for USB2PHYPeter Chen
There is an offset for USB2PHY in SALVO phy, add offset parameter for read and write API to cover both USB2 and USB3 PHY control. Signed-off-by: Peter Chen <peter.chen@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20230517161646.3418250-2-Frank.Li@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-05-17phy: qcom-qmp-usb: add support for updated qcm2290 / sm6115 bindingBhupesh Sharma
Add support for the new qcm2290 / sm6115 binding. The USB QMP phy on these devices supports 2 lanes. Note that the binding now does not describe every register subregion and instead the driver holds the corresponding offsets. While at it also include support for PCS_MISC region which was left out earlier. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Link: https://lore.kernel.org/r/20230516150511.2346357-3-bhupesh.sharma@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-05-17dt-bindings: phy: qcom,qmp-usb: Drop legacy bindings and move to newer one ↵Bhupesh Sharma
(SM6115 & QCM2290) 'qcom,msm8996-qmp-usb3-phy.yaml' defines bindings for several PHYs which predate USB -> USB+DP migration. Since SM6115 and QCM2290 nodes for USB QMP phy are being added to dtsi files by followup patches, move these bindings instead to the newer style 'qcom,sc8280xp-qmp-usb3-uni-phy.yaml' file. Since no device trees use these bindings presently, so we have no ABI breakages with this patch. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Link: https://lore.kernel.org/r/20230516150511.2346357-2-bhupesh.sharma@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-05-16phy: ti: gmii-sel: Enable USXGMII mode for J784S4Siddharth Vadapalli
TI's J784S4 SoC supports USXGMII mode with the CPSW9G instance's MAC ports 1 and 2. Add USXGMII mode to the extra_modes member of J784S4's SoC data. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230331062521.529005-3-s-vadapalli@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-05-16phy: ti: gmii-sel: Add support for CPSW9G GMII SEL in J784S4Siddharth Vadapalli
Each of the CPSW9G ports in TI's J784S4 SoC support modes such as QSGMII. Add a new compatible for it and allow the usage of "ti,qsgmii-main-ports" property for J784S4. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230331062521.529005-2-s-vadapalli@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-05-16phy: ti: gmii-sel: Enable SGMII mode for J721ESiddharth Vadapalli
TI's J721E SoC supports SGMII mode with the CPSW9G instance of the CPSW Ethernet Switch. Thus, enable it by adding SGMII mode to the list of the corresponding extra_modes member. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230309063514.398705-4-s-vadapalli@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-05-16phy: ti: gmii-sel: Enable SGMII mode for J7200Siddharth Vadapalli
TI's J7200 SoC supports SGMII mode with the CPSW5G instance of the CPSW Ethernet Switch. Thus, enable it by adding SGMII mode to the list of the corresponding extra_modes member. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230309063514.398705-3-s-vadapalli@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-05-16phy: ti: gmii-sel: Add support for SGMII modeSiddharth Vadapalli
Add support to configure the CPSW MAC's PHY in SGMII mode if the SoC supports it. The extra_modes member of the phy_gmii_sel_soc_data struct corresponding to the SoC is used to determine whether or not the SoC supports SGMII mode. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230309063514.398705-2-s-vadapalli@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-05-16phy: freescale: imx8m-pcie: Use devm_platform_ioremap_resource()Yang Li
Convert platform_get_resource(),devm_ioremap_resource() to a single call to devm_platform_ioremap_resource(), as this is exactly what this function does. Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Link: https://lore.kernel.org/r/20230428052758.38636-1-yang.lee@linux.alibaba.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-05-16phy: qcom-snps: correct struct qcom_snps_hsphy kerneldocKrzysztof Kozlowski
Update kerneldoc of struct qcom_snps_hsphy to fix: drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c:135: warning: Function parameter or member 'update_seq_cfg' not described in 'qcom_snps_hsphy' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230507144818.193039-1-krzysztof.kozlowski@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-05-16phy: amlogic: phy-meson-g12a-mipi-dphy-analog: fix CNTL2_DIF_TX_CTL0 valueNeil Armstrong
Use the same CNTL2_DIF_TX_CTL0 value used by the vendor, it was reported fixing timings issues. Fixes: 2a56dc650e54 ("phy: amlogic: Add G12A Analog MIPI D-PHY driver") Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230512-amlogic-v6-4-upstream-dsi-ccf-vim3-v4-10-2592c29ea263@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-05-16phy: mediatek: rework the floating point comparisons to fixed pointTom Rix
gcc on aarch64 reports drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c: In function ‘mtk_hdmi_pll_set_rate’: drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c:240:52: error: ‘-mgeneral-regs-only’ is incompatible with the use of floating-point types 240 | else if (tmds_clk >= 54 * MEGA && tmds_clk < 148.35 * MEGA) Floating point should not be used, so rework the floating point comparisons to fixed point. Signed-off-by: Tom Rix <trix@redhat.com> Reviewed-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/20230502145005.2927101-1-trix@redhat.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-05-16phy: hisilicon: Allow building phy-hisi-inno-usb2 on ARM32David Yang
Support for inno-usb2-phy on Hi3798MV100 was added into existing driver, while Hi3798MV100 is a A9 ARM32-only SoC. Signed-off-by: David Yang <mmyangfl@gmail.com> Link: https://lore.kernel.org/r/20230509060449.1151113-3-mmyangfl@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-05-16phy: hisilicon: Add inno-usb2-phy driver for Hi3798MV100David Yang
Adopt existing phy-hisi-inno-usb2 driver to Hi3798MV100, with a slightly different TEST register convention. Signed-off-by: David Yang <mmyangfl@gmail.com> Link: https://lore.kernel.org/r/20230509060449.1151113-2-mmyangfl@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-05-16phy: Revert "phy: Remove SOC_EXYNOS4212 dep. from PHY_EXYNOS4X12_USB"Artur Weber
Support for the Exynos4212 SoC was originally dropped as there were no boards using it. We will be adding a device that uses it, so add it back. This reverts commit fee7e1d50c6e6da1d99035181ba5a5c88f5bb526. Signed-off-by: Artur Weber <aweber.kernel@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230501195525.6268-9-aweber.kernel@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-05-16phy: qcom: qmp: Update IPQ9574 USB Phy initialization SequenceVaradarajan Narayanan
Updated USB QMP PHY Init sequence based on HPG for IPQ9574. Reused clock and reset list from existing targets. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Link: https://lore.kernel.org/r/4f15c21f28e2a1332fbdb04d60641cbbf05c6f15.1683630932.git.quic_varada@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-05-16phy: qcom-qusb2: add QUSB2 support for IPQ9574Varadarajan Narayanan
Add the phy init sequence for the Super Speed ports found on IPQ9574. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Link: https://lore.kernel.org/r/7c67e9e92227add6544009092adbd400c3cb47db.1683630932.git.quic_varada@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-05-16dt-bindings: phy: qcom,qmp-usb: Add IPQ9574 USB3 PHYVaradarajan Narayanan
* Add dt-bindings for USB3 PHY found on Qualcomm IPQ9574 * Making power-domains as optional since IPQ9574 doesn't have GDSCs Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/064614c5b28f6d813634ad14a59b0bf94ac334b7.1683630932.git.quic_varada@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-05-16dt-bindings: phy: qcom,qusb2: Document IPQ9574 compatibleVaradarajan Narayanan
Document the compatible string used for the qusb2 phy in IPQ9574. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Link: https://lore.kernel.org/r/d55c95a6bfeef3f49fdbcde9bc97157374e81a65.1683630932.git.quic_varada@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-05-08phy: sparx5-serdes: add skip_cmu_cfg check when configuring lanesDaniel Machon
Add a check for skip_cmu_cfg when configuring the serdes lane. All individual serdeses are reset upon first configuration. Resetting the serdes involves reconfiguring it with preset values. The serdesmode is required to determine the clock-providing CMU, therefore make sure the serdes is not reconfigured if the serdesmode is not set. Signed-off-by: Daniel Machon <daniel.machon@microchip.com> Link: https://lore.kernel.org/r/20230417180335.2787494-8-daniel.machon@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-05-08phy: sparx5-serdes: remove power up of all CMUsDaniel Machon
CMUs should not be powered up by default anymore, so remove responsible code. Signed-off-by: Daniel Machon <daniel.machon@microchip.com> Link: https://lore.kernel.org/r/20230417180335.2787494-7-daniel.machon@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-05-08phy: sparx5-serdes: power on CMUs individuallyDaniel Machon
Power on the CMU instance, that provides the clock for the serdes, given the specified serdes mode and index. The CMU instance is looked up, using a preset map of serdes mode and index to CMU index. Signed-off-by: Daniel Machon <daniel.machon@microchip.com> Link: https://lore.kernel.org/r/20230417180335.2787494-6-daniel.machon@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-05-08phy: sparx5-serdes: power down all CMUs by defaultDaniel Machon
All CMUs are powered up initially. This uses needless power. This patch makes sure all CMUs are powered down by default. This involves configuring a number reference clock and power-down registers of the CMU. Individual CMUs are later powered up, when the serdes lanes are configured. Signed-off-by: Daniel Machon <daniel.machon@microchip.com> Link: https://lore.kernel.org/r/20230417180335.2787494-5-daniel.machon@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-05-08phy: sparx5-serdes: reorder CMU functionsDaniel Machon
Reorder CMU functions, as some of them are now required by the serdes functions. No functional changes. Signed-off-by: Daniel Machon <daniel.machon@microchip.com> Link: https://lore.kernel.org/r/20230417180335.2787494-4-daniel.machon@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-05-08phy: sparx5-serdes: configure optimal quiet mode for serdes lanesDaniel Machon
All the serdes lanes of the sparx5 will transition between normal mode and quiet mode, depending on activity. Make sure that the quiet mode is configured optimally for all lanes initially. Although not much, this will save a small amount of power. Signed-off-by: Daniel Machon <daniel.machon@microchip.com> Link: https://lore.kernel.org/r/20230417180335.2787494-3-daniel.machon@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-05-08phy: sparx5-serdes: add registers required for SD/CMU power downDaniel Machon
Add registers required to configure serdeses and CMUs for initial power down. Signed-off-by: Daniel Machon <daniel.machon@microchip.com> Link: https://lore.kernel.org/r/20230417180335.2787494-2-daniel.machon@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-05-08phy: cadence-torrent: Add USB + DP multilink configurationSwapnil Jakhade
Add USB + DP no SSC multilink configuration sequences. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20230418173157.25607-5-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-10 08:14:39 +0000